IA188EM-PQF100I-R datasheet(22/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

The value in this register determines the number of internal processor cycles in one phase (half-period) of

the 32 x serial clock.

The contents of these registers must be adjusted to reflect the new processor clock frequency if power-

save mode is in effect.

The baud rate divisor may be calculated from:

BAUDDIV = (Processor Frequency / (32 x baud rate)) -1

By setting the BAUDDIV to 0000h, the maximum baud rate of 1/32 of the internal processor frequency

clock is set. Setting BAUDDIV to 129 (81h) provides a baud rate of 9600 at 40MHz. The baud rate

tolerance is +4.6% and –1.9% with respect to the actual serial port baud rate, not the target baud rate.

Baud Rates

Divisor Based on CPU Clock Rate

Baud Rate

20 MHz

25 MHz

33 MHz

40 MHz

300

2082

2603

3471

4165

600

1040

1301

1735

2082

1200

519

650

867

1040

2400

259

324

433

519

4800

129

161

216

259

9600

107

129

14400

19200

625 Kbaud

n/a

781.25 Kbaud

n/a

1.041 Mbaud

n/a

1.25 Mbaud

n/a

The value of the SPBAUD register at reset is undefined.

7 6 5 4 3

BAUDDIV

BAUDDIV [15:0] (bits 15-0) – Baud Rate Divisor. Defines the divisor for the internal processor

clock.

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