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IA188EM-PQF100I-R 数据表(PDF) 91 Page - InnovASIC, Inc |
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IA188EM-PQF100I-R 数据表(HTML) 91 Page - InnovASIC, Inc |
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91 / 133 page  IA186EM/IA188EM Data Sheet 8/16-BIT Microcontrollers As of Production Version -03 AC Characteristics Over Commercial Operating Ranges (40 MHz) No. Name Description MIN MAX Units General Timing Requirements 1 tDVCL Data in Setup 10 ns 2 tCLDX Data in Hold 0 ns General Timing Responses 3 tCHSV Status Active Delay 0 6 ns 4 tCLSH Status Inactive Delay 0 6 ns 5 tCLAV ad Address Valid Delay 0 12 ns 6 tCLAX Address Hold 0 12 ns 8 tCHDX Status Hold Time 0 ns 9 tCHLH ale Active Delay 0 8 ns 10 tLHLL ale Width tCLCH-5 ns 11 tCHLL ale Inactive Delay 0 8 ns 12 tAVLL ad Address Valid to ale Low tCLCH ns 13 tLLAX ad Address Hold from ale Inactive tCHCL ns 14 tAVCH ad Address Valid to Clock High 0 ns 15 tCLAZ ad Address Float Delay 0 12 ns 16 tCLCSV mcs_n/pcs_n Inactive Delay 0 12 ns 17 tCXCSX mcs_n/pcs_n Hold from Command Inactive tCLCH ns 18 tCHCSX mcs_n/pcs_n Inactive Delay 0 12 ns 19 tDXDL den_n Inactive to dt_r_n Low 0 ns 20 tCVCTV Control Active Delay 1 0 10 ns 21 tCVDEX den_n Inactive Delay 0 0 ns 22 tCHCTV Control Active Delay 2 0 10 ns 23 tLHAV ale High to Address Valid 7.5 ns 80 tCLCLX lcs_n Inactive Delay 0 9 ns 81 tCLCSL lcs_n Active Delay 0 9 ns 82 tCLRF clkoutA High to rfsh_n Invalid 0 12 ns 84 tLRLL lcs_n Precharge Pulse Width tCLCL + tCLCH ns Read Cycle Timing Responses 24 tAZRL ad Address Float to rd_n Active 0 ns 25 tCLRL rd_n Active Delay 0 10 ns 26 tRLRH rd_n Pulse Width tCLCL ns 27 tCLRH rd_n Inactive Delay 0 10 ns 28 tRHLH rd_n Inactive to ale High tCLCH ns 29 tRHAV rd_n Inactive to ad Address Active tCLCL ns 30 tCLDOX Data Hold Time 0 ns Write Cycle Timing Responses 31 tCVCTX Control Inactive Delay 0 10 ns 32 tWLWH wr_n Pulse Width 2tCLCL ns 33 tWHLH wr_n Inactive to ale High tCLCH ns 3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com |
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