IA188EM-PQF100I-R datasheet(50/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

Power-Save Mode

The operation of the CPU and peripherals operate at a slower clock frequency when in power save mode

reducing power consumption and thermal dissipation. Should an interrupt occur, the microcontroller

returns to its normal operating frequency automatically on the internal clock’s next rising edge in t3. Any

clock dependent devices should be reprogrammed for the changed in frequency during the power-save

mode period.

Initialization and Reset

res_n (Reset), the highest priority interrupt, must be held low for 1mS during power-up to initialize the

microcontroller correctly. This operation makes the device cease all instruction execution and local bus

activity. The microcontoller begins instruction execution at physical address FFFF0h when res_n

becomes inactive and after an internal processing interval with ucs_n asserted and three wait states. Reset

also sets up certain registers to predetermined values and resets the Watchdog timer.

Reset Configuration Register

The data on the address/data bus (ad15 – ad0 for the Am186EM and ao15 – ao8 and ad7 – ad0 for the

Am188EM) are written into the Reset Configuration register when reset is low. This data is system

dependent and is held in the Reset Configuration register after Reset is de-asserted. This configuration

data may be placed on the address/data bus by using weak external pull-up and pull-down resistors or

applied to the bus by an external driver, as the processor does not drive the bus during reset. It is a

method of supplying the software with some initial data after a reset; for example, option jumper

positions.

Chip Selects

Chip select generation is programmable for memories and peripherals. Programming is also available to

produce ready and wait-state generation plus latched address bits a1 and a2. For all memory and I/O

cycles, the chip-select lines are active within their programmed areas, regardless of whether they are

generated by the internal DMA unit or the CPU.

There are six chip selects outputs for memories and a further six for peripherals whether in memory or I/O

space. The memory chip-selects are able to address three memory ranges, whereas the peripheral chip-

selects are used to address 256-byte blocks that are offset from a programmable base address. Writing to

a chip-select register enables the related logic even in the event that the pin in question has another

function, as for example in the case that the pin is programmed to be a PIO.

Chip Select Timing

For normal timing, the ucs_n and lcs_n outputs are asserted with the non-multiplexed address bus.

Ready and Wait-State Programming

Each of the memory or peripheral chip-select lines can have a ready signal programmed that can be the

ardy or srdy signal. The chip-select control registers (UMCS, LMCS, MMCS, PACS, and MPCS) have

a single bit that selects if the external ready signal is to be used or not (R2, bit 2). R1 & R0 (bits 1-0) in

these registers control the number of wait-states that are inserted during each access to a memory or

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