IA188EM-PQF100I-R datasheet(14/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

ST (bit 1) – Start/Stop DMA Channel. When the start bit is set to 1, the DMA channel is started. The

CHG bit must be set to 1 for this bit to be modified and only during the same register write. A

processor reset causes this bit to be set to 0.

Bn/W (bit 0) – Byte/Word Select. When set to 1, word transfers are selected. When set to 0, byte

transfers are selected. (The IA188EM does not support word transfers and furthermore they are not

supported if the chip selects are programmed for 8-bit transfers.)

D1TC (0d8h) - DMA Transfer Count Registers.

D0TC (0c8h)

The DMA Transfer Count registers are maintained by each DMA channel. They are decremented after

each DMA cycle. The state of the TC bit in the DMA control register has no influence on this activity.

But, if unsynchronized transfers are programmed or if the TC bit in the DMA control word is set, DMA

activity ceases when the transfer count register reaches 0.

The D0TC and D1TC registers are undefined at reset.

6 5 4 3

TC15 – TC0

TC [15:0] (bits 15-0) – DMA Transfer Count contains the transfer count for the respective DMA

channel. Its value is decremented after each transfer.

D1DSTH (0d6h) - The DMA DeSTination Address High Register.

D0DSTH (0c6h)

The 20-bit destination address consists of these four bits combined with the 16-bits of the respective

Destination Address Low Register. A DMA transfer requires that two complete 16-bit registers (high and

low registers) be used for both the source and destination addresses of each DMA channel involved.

These four registers must be initialized. Each address may be incremented or decremented independently

of the other after each transfer. The addresses are incremented or decremented by two for word transfers

and incremented or decremented by 1 for byte transfers.

The D0DSTH and D1DSTH registers are undefined at reset.

7 6 5 4 3

Reserved

DDA19-DDA16

Reserved [15:4] (bits 15-4) – Reserved.

DDA [19:16] (bits 3-0) – DMA Destination Address High bits are driven onto A19-A16 during the

write phase of a DMA transfer.

DIDSTL (0d4h) - DMA DeSTination Address Low Register.

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