IA188EM-PQF100I-R datasheet(66/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

pcs6_n/A2/ – Peripheral Chip Select 6 (synchronous output) / latched Address Bit 2 (synchronous

output)

pcs6_n – This signal provides an indication that a memory access is under way for the seventh region of

the peripheral memory block (I/O or memory address space). The base address of the Peripheral memory

block is programmable. pcs6_n is held high during both bus hold and reset. This output is asserted with

the ad address bus over a 256-byte range.

A2 – This pin provides and internally latched address bit 2 to the system when the EX bit (bit 7) in the

MCS_n and PCS_n auxiliary (MPCS) register is 0. It retains its previously latched value during a bus

hold.

pio31 – pio0

Programmable I/O Pins (asynchronous input/output open –drain)

32 individually programmable I/O pins are provided. See page 62.

rd_n - Read strobe (synchronous output with tristate)

This pin provides an indication to the system that a memory or I/O read cycle is under way. It will not to

be asserted before the ad bus is floated during the address to data transition. rd_n is tristated during bus

hold.

res_n - Reset (asynchronous level-sensitive input)

This pin forces a reset on the microcontroller. It has a Schmitt trigger to allow power-on reset generation

via an RC network. When this signal is asserted, the microcontroller immediately terminates its present

activity, clears its internal logic, and transfers CPU control to the reset address, FFFF0h.

res_n must be asserted for at least 1ms and may be asserted asynchronously to clkouta as it is

synchronized internally. Furthermore, Vcc must be within specification and clkouta must be stable for

more than four of its clock periods for the period that res_n is asserted.

The microcontroller starts to fetch instructions 6.5 clkouta clock periods after the deassertion of res_n.

rfsh2_n/aden_n - IA188EM only - Refresh 2 (synchronous output with tristate) / Address Enable

(input with internal pull-up)

rfsh2_n – Indicates that a DRAM refresh cycle is being performed when it is asserted low. However, this

is not valid in PSRAM mode where mcs3_n/rfsh_n is used instead.

aden_n – If this pin is held high during power-on reset, the ad bus (ao15-ao8 & ad7-ad0) is controlled

during the address portion of the LCS and UCS bus cycles by the DA bit (bit 7) in the LCS and UCS

registers. If the DA bit is 1, the address is accessed on the a19-a0 pins reducing power consumption. The

weak pull-up on this pin obviates the necessity of an external pull-up.

If this pin is held low during power-on reset, the ad bus is used for both addresses and data without regard

for the setting of the DA bits. rfsh2_n/aden_n is sampled one crystal clock cycle after the rising edge of

res_n and is tristated during bus holds and ONCE mode.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

IA188EM-PQF100I-R 数据表(PDF) 66 Page - InnovASIC, Inc

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