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IA188EM-PQF100I-R 数据表(PDF) 16 Page - InnovASIC, Inc |
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IA188EM-PQF100I-R 数据表(HTML) 16 Page - InnovASIC, Inc |
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16 / 133 page ![]() IA186EM/IA188EM Data Sheet 8/16-BIT Microcontrollers As of Production Version -03 DSA [15:0] (bits 15-0) – DMA Source Address Low bits are placed onto a15-a0 during the read phase of a DMA transfer. MPCS (0a8h) - MCS and PCS Auxiliary Register. This register controls more than one type of chip select, making it different from the other chip select control registers. The MPCS register contains information for the following, mcs3_n - mcs0_n as well as pcs6_n - pcs5_n and pcs3_n - pcs0_n. The MPCS register also contains a bit that configures the pcs6_n - pcs5_n pins as either chip selects or as alternate sources for the A2 and A1 address bits. Either address bits a1 & a2 or pcs6_n - pcs5_n are selected to the exclusion of the other. When programmed for address bits, these outputs can be used to provide latched address bits for a2 & a1 pcs6_n - pcs5_n are high and not active on processor reset. An access to the MPCS register causes the pins to activate, when the pcs6_n - pcs5_n are configured as address pins. The pcs6_n - pcs5_n pins do not require corresponding access to the PACS register to be activated. The value of the MPCS register is undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 M6-M0 EX MS 1 1 1 R2 R1-R0 Reserved (bit 15) – Set to 1. M [6:0] (bits14-8) MCS_n Block Size – These seven bits determine the total block size for the MCS3_n - MCS0_n chip selects. The total block size is divided equally among the four chip selects. The following table shows the relationship between M [6:0] and the size of the memory block. Total Block Size Individual Select Size M6 – M0 8K 2K 0000001b 16K 4K 0000010b 32K 8K 0000100b 64K 16K 0001000b 128K 32K 0010000b 256K 64K 0100000b 512K 128K 1000000b EX (bit7) Pin Selector – This bit determines whether the pcs6_n - pcs5_n pins are configured as chip selects or as alternate outputs for a2 & a1. When this bit is set to 1, pcs6_n - pcs5_n are configured as peripheral chip select pins, whereas when set to 0, pcs6_n - pcs5_n become address bit a1 and address bit a2 respectively. 3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com |
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