IA188EM-PQF100I-R datasheet(46/133 Pages) INNOVASIC

46 / 133 page

IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

The CPU shifts left 2 bits (multiplies by 4) an 8-bit interrupt type, generated by the interrupt controller, to

produce an offset into the interrupt vector table.

The INTVEC register is undefined at reset.

T4 – T0

Reserved (bits 15-8) – Read as 0.

T [4:0] (bits 7-3) – Interrupt Type. These five bits contain the five most significant bits of the

interrupt types used for the internal interrupt type. The least significant three bits of the interrupt type

are supplied by the interrupt controller, as set by the priority level of the interrupt request.

Reserved (bits 2-0) – Read as 0.

SSR (018h) – Synchronous Serial Receive Register.

This register holds the serial data received on the SSI port.

The value of the SSR register is undefined at reset.

Reserved

SR7-SR0

Reserved (bits 15-8) – Reserved Bits.

SR[7:0] (bits 7-0) – Data received over the SDATA pin.

SSD0 (016h) – Synchronous Serial Transmit Registers.

SSD0 (014h)

These registers hold the data to be transmitted by the SSI ports.

The value of these registers is undefined at reset.

Reserved

SD7-SD0

Reserved (bits 15-8) – Reserved Bits.

SD[7:0] (bits 7-0) – Data to be transmitted over the SDATA pin.

SSC (012h) – Synchronous Serial Control Register.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

IA188EM-PQF100I-R 数据表(PDF) 46 Page - InnovASIC, Inc