IA188EM-PQF100I-R datasheet(51/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

peripheral location (from 0 to 3). The control registers for pcs3_n – pcs0_n utilize three bits, R3, R1 – R0

(bits 3, 1 – 0) to provide 5, 7, 9, and 15 wait-states in addition to the original values of 0 – 3 wait states.

In the case where an external ready has been selected as required, internally programmed

wait-states will always be completed before the external ready can finish or extend a bus cycle. As an

example, consider a system in which the number of wait-states to be inserted has been set to three. The

external ready pin is sampled by the processor during the first wait cycle. The access is completed after

seven cycles (4 cycles plus 3 wait-cycles) if the ready is asserted. Alternatively, if the ready is not asserted

during the first wait cycle the access is prolonged until ready is asserted and two more wait-states are

inserted followed by t4.

Chip Select Overlap

Overlapping chip selects are those configurations in which more than one chip-select is asserted for the

same physical address. For example, if PCS is configured in I/O space with LCS or any other chip select

configured for memory, address 00000h is not overlapping the chip selects. It is not recommended that

multiple chip-select signals be asserted for the same physical address, although it may be inescapable in

certain systems. If this is the case, then all overlapping chip-selects must have the same external ready

configuration and the same number of wait-states to be inserted into access cycles.

Internal signals are employed to access the peripheral control block (PCB) and these signals serve as chip

selects that are configured with no wait-states and no external ready. Therefore, the PCB can be

programmed with addresses that overlap external chip-selects only if these chip selects are configured in

the same manner.

Care should be exercised in the use of the Disable Address (DA) bit in the LMCS or UMCS registers

when overlapping an additional chip-select with either the lcs_n or ucs_n chip-selects. Setting the DA bit

to 1 prevents the address from being driven onto the AD bus for all accesses for which the respective

chip-select is active, including those accesses for which the multiple selects are active.

The mcs_n and pcs_n pins are dual-purpose pins, either as chip-selects or PIO inputs or outputs.

However, their respective ready and wait-state configurations for their chip-select function will be in

effect no matter for which function these two pins are actually programmed. This requires that even if

these pins are configured as PIO and enabled (by writing to the MMCS and MPCS registers for the

mcs_n chip-selects and to the PACS and MPCS registers for the pcs_n chip-selects), the ready and wait-

state settings for these signals must agree with the settings for any over-lapping chip-selects as if they had

been configured as chip-selects.

Even though pcs4_n is not available as an external pin it has ready and wait-state logic and must therefore

follow the rules for overlapping chip-selects. pcs6_n and pcs5_n on the other hand have ready and wait-

state logic that is disabled when these pins are configured as address bits a2 and a1 respectively.

If the chip-select configuration rules are not followed, the processor may hang with the appearance of

waiting for a ready signal even in a system in which ready (ardy or srdy) is always set to 1.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

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