IA188EM-PQF100I-R datasheet(31/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

P (bit 3) – Prescaler Bit. P is ignored if external clocking is enabled (EXT = 1). Timer 2 prescales the

timer when P is set to 1. Otherwise, the timer is incremented on every fourth CLKOUT cycle.

EXT (bit 2) – External Clock Bit. This bit determines whether an external or internal clock is used.

EXT = 1, an external clock is used and EXT = 0, an internal is used.

ALT (bit 1) – Alternate Compare Bit. If set to 1, the timer will count to Maxcount Compare A, reset

the count register to 0, count to maxcount compare B, reset the count register to 0 and begin again at

maxcount compare A.

If set to 0, the timer will count to maxcount compare A, reset the count register to 0, and begin again

at maxcount compare A. Maxcount compare B is not used in this case.

CONT (bit 0) – Continuous Mode Bit. The timer will run continuously when this bit is set to 1. The

timer will stop after each count run and EN will be cleared if the CONT bit is set to 0. If CONT = 1

and ALT = 1, the respective timer counts to the maxcount compare A value and resets, then

commences counting to maxcount compare B value, resets and ceases counting.

T2CON (066h) - Timer 2 Mode and CONtrol Register.

This register controls the operation of the Timer 2.

The value of the T2CON register is 0000h at reset.

EN INHn INT

CONT

EN (bit 15) – Enable Bit. The timer is enabled when the EN bit is 1. The timer count is inhibited

when the EN bit is 0. Setting this bit to 1 by writing to the T2CON register requires that the INH bit be

set to 1 during the same write. This bit is write-only, but with the INHn bit set to 1 in the same write

operation.

INHn (bit 14) – Inhibit Bit. Gates the setting of the enable (EN) bit. This bit must be set to 1 in the

same write operation that sets the enable (EN) bit. This bit always reads as 0.

INT (bit 13) – Interrupt Bit. An interrupt request is generated, by setting the INT bit to 1, when the

Count register reaches its maximum, MC = 1.

Reserved (bits 12-6) – Set to 0.

MC (bit 5) – Maximum Count. When the timer reaches its maximum count this bit is set to 1,

regardless of the interrupt enable bit. This bit may be used by software polling to monitor timer status

rather than through interrupts if desired.

Reserved (bits 4-1) – Set to 0.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

IA188EM-PQF100I-R 数据表(PDF) 31 Page - InnovASIC, Inc

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