IA188EM-PQF100I-R datasheet(25/133 Pages) INNOVASIC

25 / 133 page

IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

RXIE (bit 10) – Receive Data Ready Interrupt Enable. This bit enables the generation of an interrupt

requests whenever the receive register contains valid data (RDR bit 1). The respective port does not

generate interrupts when this bit is 0. Interrupts continue to be generated as long as RDR and the

RXIE are 1.

LOOP (bit 9) – Loop-back. The serial port is placed into the loop-back mode when this bit is set.

BRK (bit 8) – Send Break. When this bit is set to 1, the txd pin is driven low, overriding any data that

may be in the course of being shifted out of the transmit shift register.

See the definitions of long and short break in the Serial Port Status register definition.

BRKVAL (bit 7) – Break Value. This is the ninth data bit transmitted when in modes 2 and 3. This bit

is cleared at each transmitted word and is not buffered. To transmit data with this bit set high, the

following procedure is recommended.

1. The TEMT bit in the serial port status register must go high.

2. Set the TB8 bit by writing it to the serial port control register.

3. Finally write the transmit character to the serial port transmit register.

Serial port 0 is a special case in that if this bit is 1, the associated pins are used for flow control

overriding the Peripheral Chip Select signals. This bit is 0 at reset.

PMODE (bits6:5) – Parity Mode. When this bit is set to 1, the txd pin is driven low overriding any

data that may be in the course of being shifted out of the transmit shift register.

See the definitions of long and short break in the Serial Port Status register definition.

WLGN (bit 4) – Word Length. The number of bits transmitted or received in a frame is determined by

the value of this bit. When this bit is 0, the number of data bits in a frame is 7 whereas when this bit is

1 the number of data bits in a frame is 8. This bit is 0 at reset.

STP (bit 3) – Stop Bits. This bit specifies the number of stop bits used to indicate the end of a frame.

When this bit is 0, the number of stop bits is 1. When it is 1, the number of stop bits is 2. This bit is 0

at reset.

TMODE (bit 2) – Transmit Mode. The transmit section of the serial port is enabled when this bit is 1

and disabled when this bit is 0.

RSIE (bit 1) – Receive Status Interrupt Enable. When an exception occurs during data reception an

interrupt request is generated if enabled by this bit (RSIE = 1). Interrupt requests are made for the

error conditions listed (BRK, OER, PER, and FER) in the serial port status register. This bit is 0 at

reset.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

IA188EM-PQF100I-R 数据表(PDF) 25 Page - InnovASIC, Inc

IA188EM-PQF100I-R 数据表(HTML) 25 Page - InnovASIC, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载