IA188EM-PQF100I-R datasheet(40/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

Slave Mode

This is a read-only register and such a read results in the status of the interrupt request bits presented to

the interrupt controller. The status of these bits is available when this register is read.

When an internal interrupt request (D1, D0, TMR2, TMR1, or TMR0) occurs, the respective bit is set to 1.

The internally generated interrupt acknowledge resets these bits.

The REQST register contains 0000h on reset.

12 11

Reserved

TMR2 TMR1 D1 D0 Res TMR0

Reserved (bits 15 – 6)

TMR2 (bit 5) Interrupt Requests. Setting this bit to 1 indicates that timer 2 has a pending interrupt.

TMR1 (bit 4) Interrupt Requests. Setting this bit to 1 indicates that timer 1 has a pending interrupt.

D1:D0 (bits 3:2) DMA Channel Interrupt Request. Setting either bit to 1 indicates that the respective

DMA channel has a pending interrupt.

Reserved (bit 1)

TMR0 (bit 0) – Timer0 Interrupt Request. Setting this bit to 1 indicates that timer 0 has a pending

interrupt.

INSERV (02ch) – IN-SERVice Register.

Master Mode

The interrupt controller sets the bits in this register when the interrupt is taken. Writing the corresponding

interrupt type to the End-of-Interrupt (EOI) register clears each of these bits.

When one of these bits is set, an interrupt request will not be generated by the microcontroller for the

respective source. This prevents an interrupt from interrupting itself if interrupts are enabled in the ISR.

This restriction is bypassed in fully Special Fully nested mode for the INT0 and INT1 sources.

The INSERV register contains 0000h on reset

Reserved

SPI WD I4 I3 I2 I1 IO D1 D0 Res TMR

Reserved (bits 15 – 11)

SPI (bit 10) – Serial Port Interrupt Request. This is the serial port 0 interrupt state.

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IA188EM-PQF100I-R 数据表(PDF) 40 Page - InnovASIC, Inc