IA188EM-PQF100I-R datasheet(69/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

After power-on-reset, ucs_n is active low and program execution begins at FFFF0h with the default

configuration of the ucs_n chip select is for 64 Kbytes memory range from F0000h to FFFFFh.

once1_n – (ONCE – ON Circuit Emulation). This pin and its companion pin once0_n define the

microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if both

are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE mode all pins

are tristated and remain so until a subsequent reset. To prevent the microcontroller from entering ONCE

mode inadvertently, this pin has a weak pull-up that is only present during reset. Finally, this pin is not

tristated during bus hold.

uzi_n/pio26 – Upper Zero Indicate (synchronous output)

This pin allows the designer to determine if an access to the interrupt vector table is in progress by ORing

it with bits 15-10 of the address and data bus (ad15-ad10 on the AI186EM and ao15-ao10 on the

AI188EM). uzi_n is the logical OR of the inverted a19-a16 bits. It asserts in the first period of a bus

cycle and is held throughout the cycle.

At reset uzi_n should be pulled high or should be allowed to float. If this pin is pulled low at reset, the

microcontroller enters a reserved clock test mode.

vcc – Power Supply (input)

These pins supply power (+5V) to the microcontroller.

whb_n – Write High Byte - IA186EM only - (synchronous output with tristate)

This pin and wlb_n provide an indication to the system of which bytes of the data bus (upper, lower or

both) are taking part in a write cycle. whb_n is asserted with ad15_ad8 and is the logical OR of bhe_n

and wr_n. It is tristated during reset.

wlb_n/wb_n – Write Low Byte - IA186EM only - (synchronous output with tristate) / Write Byte –

IA188EM only - (synchronous output with tristate)

wlb_n - wlb_n and whb_n provide an indication to the system of which bytes of the data bus (upper,

lower, or both) are taking part in a write cycle. wlb_n is asserted with ad7_ad0 and is the logical OR of

ad0 and wr_n. It is tristated during reset.

wb_n – On the IA188EM microcontroller, wb_n provides an indication that a write to the bus is

occurring. It shares the same early timing as that of the non-multiplexed address bus, and is associated

with ad7-ad0. It is tristated during reset.

wr_n – Write Strobe (synchronous output)

This pin provides an indication to the system that the data currently on the bus is to be written to a

memory or I/O device. It is tristated during a bus hold or reset.

x1 – Crystal Input (input)

This pin and x2 are the connections for a fundamental mode or third-overtone, parallel-resonant crystal

used by the internal oscillator circuit. An external clock source for the microcontroller is connected to x1

while the x2 pin is left unconnected.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

IA188EM-PQF100I-R 数据表(PDF) 69 Page - InnovASIC, Inc

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