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IA188EM-PQF100I-R 数据表(PDF) 101 Page - InnovASIC, Inc |
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IA188EM-PQF100I-R 数据表(HTML) 101 Page - InnovASIC, Inc |
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101 / 133 page  IA186EM/IA188EM Data Sheet 8/16-BIT Microcontrollers As of Production Version -03 PSRAM Read Cycle Timing No. Name Comment MIN MAX Units General Timing Requirements 1 tDVCL Data in Setup 10 NLL ns 2 tCLDX Data in Hold 0 ns General Timing Responses 5 tCLAV ad Address Valid Delay 0 12 ns 7 tCLDV Data Valid Delay 0 12 ns 8 tCHDX Status Hold Time 0 ns 9 tCHLH ale Active Delay 0 8 ns 10 tLHLL ale Width tCHCL- 5 ns 11 tCHLL ale Inactive Delay 0 8 ns 23 tLHAV ale High to Address Valid 7.5 ns 80 tCLCLX lcs_n Inactive Delay 0 9 ns 81 tCLCSL lcs_n Active Delay 0 9 ns 84 tLRLL lcs_n Precharge Pulse Width tCLCL + tCLCH ns Read Cycle Timing Responses 24 tAZRL ad Address Float to rd_n Active 0 ns 25 tCLRL rd_n Active Delay 0 10 ns 26 tRLRH rd_n Pulse Width tCLCL ns 27 tCLRH rd_n Inactive Delay 0 10 ns 28 tRHLH rd_n Inactive to ale High tCLCH ns 59 tRHDX rd_n High to Data Hold on ad Bus 0 ns 66 tAVRL a Address Valid to rd_n Low tCLCL + tCHCL 68 tCHAV clkoutA High to a Address Valid 0 8 ns 3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com |
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