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DSP56303 数据表(PDF) 203 Page - Freescale Semiconductor, Inc |
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DSP56303 数据表(HTML) 203 Page - Freescale Semiconductor, Inc |
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203 / 292 page  Operating Modes DSP56303 User’s Manual, Rev. 2 Freescale Semiconductor 9-11 9.3.2 Signal Measurement Modes The following signal measurement and pulse width modulation modes are provided: Measurement input width (Mode 4) Measurement input period (Mode 5) Measurement capture (Mode 6) Pulse width modulation (PWM) mode (Mode 7) The external signal synchronizes with the internal clock that increments the counter. This synchronization process can cause the number of clocks measured for the selected signal value to vary from the actual signal value by plus or minus one counter clock cycle. Figure 9-10. Event Counter Mode, TRM = 0 Mode 3 (internal clock): TRM = 0 N = write preload M = write compare TE (TIO pin or prescale CLK) TLR TCPR TCF (Compare Interrupt if TCIE = 1) first event M N if clock source is from TIO pin, TIO < CPUCLK + 4 Clock 1 Counter (TCR) 0N N + 1 M 0 M + 1 TOF (Overflow Interrupt if TCIE = 1) NOTE: If INV = 1, counter is clocked on 1-to-0 clock transitions, instead of 0-to-1 transitions. |
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