DSP56303 datasheet(207/292 Pages) FREESCALE

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Operating Modes

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

9-15

9.3.2.3 Measurement Capture (Mode 6)

In Mode 6, the timer counts the number of clocks that elapse between when the timer starts and

when an external signal is received. At the first appropriate transition of the external clock

detected on the TIO signal, TCSR[TCF] is set and, if the TCSR[TCIE] bit is set, a compare

interrupt is generated. The counter halts. The contents of the counter are loaded into the TCR.

The value of the TCR represents the delay between the setting of the TCSR[TE] bit and the

detection of the first clock edge signal on the TIO signal. The value of the INV bit determines

whether a high-to-low (1 to 0) or low-to-high (0 to 1) transition of the external clock signals the

end of the timing period. If the INV bit is set, a high-to-low transition signals the end of the

timing period. If INV is cleared, a low-to-high transition signals the end of the timing period.

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

Mode

Name

Function

TIO

Clock

Capture

Measurement

Input

Internal

Figure 9-15. Capture Measurement Mode, TRM = 0

Mode 6 (internal clock): TRM = 1

N = write preload

M = write compare

Clock

(CLK/2 or prescale CLK)

TLR

TCR

Counter

first event

N + 1

Interrupt Service

reads TCR; delay

NOTE: If INV = 1, a 1-to-0 edge on TIO loads TCR with count and stops the counter.

TCF (Compare Interrupt if TCIE = 1)

TIO pin

delay being measured

= M - N clock

periods

Counter stops

counting; overflow

may occur before

capture (TOF = 1)

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