DSP56303 datasheet(204/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

9-12

Freescale Semiconductor

Triple Timer Module

9.3.2.1 Measurement Input Width (Mode 4)

In Mode 4, the timer counts the number of clocks that occur between opposite edges of an input

signal. After the first appropriate transition (as determined by the TCSR[INV] bit) occurs on the

TIO

input signal, the counter is loaded with the TLR value. If TCSR[INV] is set, the timer starts

on the first high-to-low (1 to 0) signal transition on the TIO signal. If the INV bit is cleared, the

timer starts on the first low-to-high (that is, 0 to 1) transition on the TIO signal. When the first

transition opposite in polarity to the INV bit setting occurs on the TIO signal, the counter stops.

TCSR[TCF] is set and a compare interrupt is generated if the TCSR[TCIE] bit is set. The value of

the counter (which measures the width of the TIO pulse) is loaded into the TCR, which can be

read to determine the external signal pulse width. If the TCSR[TRM] bit is set, the counter is

loaded with the TLR value on the first timer clock received following the next valid transition on

the TIO input signal, and the count resumes. If TCSR[TRM] is cleared, the counter continues to

increment on each timer clock. This process repeats until the timer is disabled.

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

Mode

Name

Function

TIO

Clock

Input width

Measurement

Input

Internal

Figure 9-11. Pulse Width Measurement Mode, TRM = 1

Mode 4 (internal clock): TRM = 1

N = write preload

M = write compare

Clock

(CLK/2 or prescale CLK)

TLR

TCR

Counter

first event

N + 1

Interrupt Service

reads TCR; width

NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO

TCF (Compare Interrupt if TCIE = 1)

TIO pin

width being measured

stops the counter and loads TCR with the count.

= M - N clock

periods

Next 0-to-1 edge

on TIO loads

counter and

process repeats

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