DSP56303 datasheet(213/292 Pages) FREESCALE

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Triple Timer Module Programming Model

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

9-21

9.3.5 Special Cases

The following special cases apply during wait and stop state.

Timer behavior during wait. Timer clocks are active during the execution of the wait

instruction and timer activity is undisturbed. If a timer interrupt is generated, the

DSP56303 leaves the wait state and services the interrupt.

Timer behavior during stop. During execution of the stop instruction, the timer clocks are

disabled, timer activity stops, and the TIO signals are disconnected. Any external changes

that happen to the TIO signals are ignored when the DSP56303 is in stop state. To ensure

correct operation, disable the timers before the DSP56303 is placed in stop state.

9.3.6 DMA Trigger

Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered by a

timer event. The timer issues a DMA trigger on every event in all modes of operation. To ensure

that all DMA triggers are serviced, provide for the preceding DMA trigger to be serviced before

the DMA channel receives the next trigger.

9.4 Triple Timer Module Programming Model

The timer programming model in Figure 9-20 shows the structure of the timer registers.

9.4.1 Prescaler Counter

The prescaler counter is a 21-bit counter that decrements on the rising edge of the prescaler input

clock. The counter is enabled when at least one of the three timers is enabled (that is, one or more

of the timer enable bits are set) and is using the prescaler output as its source (that is, one or more

of the PCE bits are set).

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