DSP56303 datasheet(179/292 Pages) FREESCALE

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SCI Programming Model

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

8-11

REIE

SCKP

STIR

TMIE

TIE

RIE

ILIE

76543

210

WOMS

RWU

WAKE

SBK

SSFTD

WDS2

WDS1

WDS0

—Reserved bit; read as 0; write to 0 for future compatibility.

Figure 8-3. SCI Control Register (SCR)

Table 8-2. SCI Control Register (SCR) Bit Definitions

Bit

Number

Bit

Name

Reset

Value

Description

23–17

Reserved. Write to 0 for future compatibility.

REIE

Receive with Exception Interrupt Enable

Enables/disables the SCI receive data with exception interrupt. If REIE is cleared, the

receive data with exception interrupt is disabled. If both REIE and RDRF are set, and PE,

FE, and OR are not all cleared, the SCI requests an SCI receive data with exception

interrupt from the interrupt controller. Either a hardware RESET signal or a software

RESET instruction clears REIE.

SCKP

SCI Clock Polarity

Controls the clock polarity sourced or received on the clock signal (SCLK), eliminating

the need for an external inverter. When SCKP is cleared, the clock polarity is positive;

when SCKP is set, the clock polarity is negative. In Synchronous mode, positive polarity

means that the clock is normally positive and transitions negative during valid data.

Negative polarity means that the clock is normally negative and transitions positive

during valid data. In Asynchronous mode, positive polarity means that the rising edge of

the clock occurs in the center of the period that data is valid. Negative polarity means that

the falling edge of the clock occurs during the center of the period that data is valid.

Either a hardware RESET signal or a software RESET instruction clears SCKP.

STIR

Timer Interrupt Rate

Controls a divide-by-32 in the SCI Timer interrupt generator. When STIR is cleared, the

divide-by-32 is inserted in the chain. When STIR is set, the divide-by-32 is bypassed,

thereby increasing timer resolution by a factor of 32. Either a hardware RESET signal or

a software RESET instruction clears this bit. To ensure proper operation of the timer,

STIR must not be changed during timer operation (that is, if TMIE = 1).

TMIE

Timer Interrupt Enable

Enables/disables the SCI timer interrupt. If TMIE is set, timer interrupt requests are sent

to the interrupt controller at the rate set by the SCI clock register. The timer interrupt is

automatically cleared by the timer interrupt acknowledge from the interrupt controller.

This feature allows DSP programmers to use the SCI baud rate generator as a simple

periodic interrupt generator if the SCI is not in use, if external clocks are used for the SCI,

or if periodic interrupts are needed at the SCI baud rate. The SCI internal clock is divided

by 16 (to match the 1

× SCI baud rate) for timer interrupt generation. This timer does not

require that any SCI signals be configured for SCI use to operate. Either a hardware

RESET signal or a software RESET instruction clears TMIE.

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