DSP56303 datasheet(182/292 Pages) FREESCALE

182 / 292 page

DSP56303 User’s Manual, Rev. 2

8-14

Freescale Semiconductor

Serial Communication Interface (SCI)

SBK

Send Break

A break is an all-zero word frame—a start bit 0, characters of all zeros (including any

parity), and a stop bit 0 (that is, ten or eleven zeros, depending on the mode selected). If

SBK is set and then cleared, the transmitter finishes transmitting the current frame,

sends 10 or 11 0s, and reverts to idle or sending data. If SBK remains set, the transmitter

continually sends whole frames of 0s (10 or 11 bits with no stop bit). At the end of the

break code, the transmitter sends at least one high (set) bit before transmitting any data

to guarantee recognition of a valid start bit. Break can signal an unusual condition,

message, and so on, by forcing a frame error; the frame error is caused by a missing

stop bit.

SSFTD

SCI Shift Direction

Determines the order in which the SCI data shift registers shift data in or out: MSB first

when set, LSB first when cleared. The parity and data type bits do not change their

position in the frame, and they remain adjacent to the stop bit.

2–0

WDS

Word Select

Select the format of transmitted and received data. Asynchronous modes are compatible

with most UART-type serial devices, and they support standard RS-232 communication

links. Multidrop Asynchronous mode is compatible with the MC68681 DUART, the

M68HC11 SCI interface, and the Intel 8051 serial interface. Synchronous data mode is

essentially a high-speed shift register for I/O expansion and stream-mode channel

interfaces. You can synchronize data by using a gated transmit and receive clock

compatible with the Intel 8051 serial interface mode 0. When odd parity is selected, the

transmitter counts the number of ones in the data word. If the total is not an odd number,

the parity bit is set, thus producing an odd number. If the receiver counts an even number

of ones, an error in transmission has occurred. When even parity is selected, an even

number must result from the calculation performed at both ends of the line, or an error in

transmission has occurred.

WDS2

WDS1

WDS0

Mode

Word Formats

8-Bit Synchronous Data (shift register mode)

Reserved

10-Bit Asynchronous (1 start, 8 data, 1 stop)

Reserved

11-Bit Asynchronous

(1 start, 8 data, 1 even parity, 1 stop)

11-Bit Asynchronous

(1 start, 8 data, 1 odd parity, 1 stop)

11-Bit Multidrop Asynchronous

(1 start, 8 data, 1 data type, 1 stop)

Reserved

Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued)

Bit

Number

Bit

Name

Reset

Value

Description

DSP56303 数据表(PDF) 182 Page - Freescale Semiconductor, Inc

DSP56303 数据表(HTML) 182 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

DSP56303 数据表(PDF) 182 Page - Freescale Semiconductor, Inc

DSP56303 数据表(HTML) 182 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载