DSP56303 datasheet(189/292 Pages) FREESCALE

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SCI Programming Model

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

8-21

In Asynchronous mode, the start bit, the eight data bits, the address/data indicator bit or the parity

bit, and the stop bit are received, respectively. Data bits are sent LSB first if SSFTD is cleared,

and MSB first if SSFTD is set. In Synchronous mode, a gated clock provides synchronization. In

either Synchronous or Asynchronous mode, when a complete word is clocked in, the contents of

the shift register can be transferred to the SRX and the flags; RDRF, FE, PE, and OR are changed

appropriately. Because the operation of the receive shift register is transparent to the DSP, the

contents of this register are not directly accessible to the programmer.

8.6.4.2 SCI Transmit Register (STX)

The transmit data register is a one-byte-wide register mapped into four addresses as STXL,

STXM, STXH, and STXA. In Asynchronous mode, when data is to be transmitted, STXL,

STXM, and STXH are used. When STXL is written, the low byte on the data bus is transferred to

the STX. When STXM is written, the middle byte is transferred to the STX. When STXH is

written, the high byte is transferred to the STX. This structure makes it easy for the programmer

to unpack the bytes in a 24-bit word for transmission. TDXA should be written in 11-bit

asynchronous multidrop mode when the data is an address and the programmer wants to set the

ninth bit (the address bit). When STXA is written, the data from the low byte on the data bus is

stored in it. The address data bit is cleared in 11-bit asynchronous multidrop mode when any of

STXL, STXM, or STXH is written. When either STX (STXL, STXM, or STXH) or STXA is

written, TDRE is cleared.

The transfer from either STX or STXA to the transmit shift register occurs automatically, but not

immediately, after the last bit from the previous word is shifted out; that is, the transmit shift

to four serial clock cycles occurs between when the data is transferred from either STX or STXA

to the transmit shift register and when the first bit appears on the TXD signal. (A serial clock cycle

is the time required to transmit one data bit.)

The transmit shift register is not directly addressable, and there is no dedicated flag for this

consecutively to STX or STXA without polling, because the second byte might overwrite the first

byte. Thus, you should always poll the TDRE flag prior to writing STX or STXA to prevent

overruns unless transmit interrupts are enabled. Either STX or STXA is usually written as part of

the interrupt service routine. An interrupt is generated only if TDRE is set. The transmit shift

In Synchronous mode, data is synchronized with the transmit clock. That clock can have either an

internal or external source, as defined by the TCM bit in the SCCR. The length and format of the

serial word is defined by the WDS0, WDS1, and WDS2 control bits in the SCR. In

Asynchronous mode, the start bit, the eight data bits (with the LSB first if SSFTD = 0 and the

MSB first if SSFTD = 1), the address/data indicator bit or parity bit, and the stop bit are

transmitted in that order. The data to be transmitted can be written to any one of the three STX

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