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DSP56303 数据表(PDF) 190 Page - Freescale Semiconductor, Inc

部件名 DSP56303
功能描述  DSP56303 USER?셎 MANUAL
PDF  292 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

DSP56303 数据表(HTML) 190 Page - Freescale Semiconductor, Inc

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DSP56303 User’s Manual, Rev. 2
8-22
Freescale Semiconductor
Serial Communication Interface (SCI)
addresses. If SCKP is set and SSHTD is set, SCI Synchronous mode is equivalent to the SSI
operation in 8-bit data on-demand mode.
Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of those status
bits within the next two cycles, the bit does not reflect its current status. For details see
the DSP56300 Family Manual.
8.7 GPIO Signals and Registers
Three registers control the GPIO functionality of the SCI pins: Port E control register (PCRE),
Port E direction register (PRRE) and Port E data register (PDRE).
8.7.1 Port E Control Register (PCRE)
The read/write PCRE controls the functionality of SCI GPIO signals. Each of the PCRE[2–0] bits
controls the functionality of the corresponding port signal. When a PCRE[i] bit is set, the
corresponding port signal is configured as an SCI signal. When a PC[i] bit is cleared, the
corresponding port signal is configured as a GPIO signal. A hardware RESET signal or a software
RESET instruction clears all PCRE bits.
8.7.2 Port E Direction Register (PRRE)
The read/write PRRE controls the direction of SCI GPIO signals. When port signal[i] is
configured as GPIO, PRRE[i] controls the port signal direction. When PRRE[i] is set, the GPIO
port signal[i] is configured as output. When PRRE[i] is cleared, the GPIO port signal[i] is
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9876543210
PE2/
SCLK
PE1/
TXD
PE0/
RXD
Note:
For bits 2–0, a 0 selects PEn as the signal and a 1 selects the specified SCI signal.
= Reserved. Read as zero. Write to zero for future compatibility.
Figure 8-8. Port E Control Register (PCRE X:$FFFF9F)



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