数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

DSP56303 数据表(PDF) 187 Page - Freescale Semiconductor, Inc

部件名 DSP56303
功能描述  DSP56303 USER?셎 MANUAL
PDF  292 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

DSP56303 数据表(HTML) 187 Page - Freescale Semiconductor, Inc

Back Button DSP56303 Datasheet HTML 183Page - Freescale Semiconductor, Inc DSP56303 Datasheet HTML 184Page - Freescale Semiconductor, Inc DSP56303 Datasheet HTML 185Page - Freescale Semiconductor, Inc DSP56303 Datasheet HTML 186Page - Freescale Semiconductor, Inc DSP56303 Datasheet HTML 187Page - Freescale Semiconductor, Inc DSP56303 Datasheet HTML 188Page - Freescale Semiconductor, Inc DSP56303 Datasheet HTML 189Page - Freescale Semiconductor, Inc DSP56303 Datasheet HTML 190Page - Freescale Semiconductor, Inc DSP56303 Datasheet HTML 191Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 187 / 292 page
background image
SCI Programming Model
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor
8-19
and the external clock is used if the SCI is the slave device, as noted above. The clock is gated
and limited to a maximum frequency equal to one eighth of the DSP core operating frequency
(that is, 12.5 MHz for a DSP core frequency of 100 MHz).
For asynchronous operation, the SCI can use the internal and external clocks in any combination
as the source clocks for the TX clock and RX clock. If an external clock is used for the SCLK
input, it must be sixteen times the desired bit rate (designated as the 16
× clock), as indicated in
Figure 8-6. When the internal clock is used to supply a clock to an external device, the clock can
use the actual bit rate (designated as the 1
× clock) or the 16 × clock rate, as determined by the
COD bit. The output clock is continuous.
When SCKP is cleared, the transmitted data on the TXD signal changes on the negative edge of
the serial clock and is stable on the positive edge. When SCKP is set, the data changes on the
positive edge and is stable on the negative edge. The received data on the RXD signal is sampled
on the positive edge (if SCKP = 0) or on the negative edge (if SCKP = 1) of the serial clock.
8.6.4 SCI Data Registers
The SCI data registers are divided into two groups: receive and transmit, as shown in Figure 8-7.
There are two receive registers: a Receive Data Register (SRX) and a serial-to-parallel Receive
Shift Register. There are also two transmit registers: a Transmit Data Register (called either STX
or STXA) and a parallel-to-serial Transmit Shift Register.
Figure 8-6. 16 x Serial Clock
RX, TX Data
(SSFTD = 0)
Idle Line
Start
Select 8-or 9-bit Words
x1 Clock
x16 Clock
(SCKP = 0)
1
0
234567
8
Stop
Start



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com