DSP56303 datasheet(195/292 Pages) FREESCALE

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Operation

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

9-3

9.2 Operation

This section discusses the following timer basics:

Reset

Initialization

Exceptions

9.2.1 Timer After Reset

A hardware RESET signal or software reset instruction clears the Timer Control and Status

enable bit 0 (TCSR[TE]) in the specific timer TCSR is set.

9.2.2 Timer Initialization

To initialize a timer, do the following:

Ensure that the timer is not active either by sending a reset or clearing the TCSR[TE]

bit.

Configure the control register (TCSR) to set the timer operating mode. Set the interrupt

enable bits as needed for the application.

Figure 9-2. Timer Module Block Diagram

GDB

Control/Status

TCSR

Counter

Timer interrupt/DMA request

Timer Control

CLK/2

TIO

Compare

TCPR

Logic

Load

Count

TLR

Prescaler CLK

TCR

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