DSP56303 datasheet(196/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

9-4

Freescale Semiconductor

Triple Timer Module

Configure other registers: Timer Prescaler Load Register (TPLR), Timer Load Register

(TLR), and Timer Compare Register (TCPR) as needed for the application.

Enable the timer by setting the TCSR[TE] bit.

9.2.3 Timer Exceptions

Each timer can generate two different exceptions:

Timer Overflow (highest priority) — Occurs when the timer counter reaches the overflow

value. This exception sets the TOF bit. TOF is cleared when a value of one is written to it

or when the timer overflow exception is serviced.

Timer Compare (lowest priority) — Occurs when the timer counter reaches the value

given in the Timer Compare Register (TCPR) for all modes except measurement modes.

In measurement modes 4–6, a compare exception occurs when the appropriate transition

occurs on the TIO signal. The Compare exception sets the TCF bit. TCF is cleared when a

value of one is written to it or when the timer compare interrupt is serviced.

To configure a timer exception, perform the following steps. The example at the right of each

step shows the register settings for configuring a Timer 0 compare interrupt. The order of the

steps is optional except that the timer should not be enabled (step 2e) until all other exception

configuration is complete:

Configure the interrupt service routine (ISR):

Load vector base address register

VBA (b23–8)

Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,

I_VEC must be defined for the assembler before the interrupt equate file is

included.

Load the exception vector table entry: two-word fast interrupt, or jump/branch to

subroutine (long interrupt).

p:TIM0C

Configure the interrupt trigger:

Enable and prioritize overall peripheral interrupt functionality.

IPRP (TOL[1–0])

Enable a specific peripheral interrupt.

TCSR0 (TCIE)

Unmask interrupts at the global level.

SR (I[1–0])

Configure a peripheral interrupt-generating function.

TCSR0 (TC[7–4])

Enable peripheral and associated signals.

TCSR0 (TE)

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