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ADE9178 数据表(PDF) 120 Page - Analog Devices

部件名 ADE9178
功能描述  Energy Management DSP with PEN Fault Detection
PDF  122 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE9178 数据表(HTML) 120 Page - Analog Devices

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Data Sheet
ADE9178
REGISTER DETAILS: ADE9178
analog.com
Rev. A | 120 of 122
Table 34. ADE9178 Register Details (Continued)
Addr
Name
Bits
Bit Name
Settings
Description
Reset
Access
when one or more bits of
STATUS2 register of ADC1 are
set.
13
ADC1_STATUS1
ADC1 STATUS1 Bit Mask. Set
this bit to enable an interrupt
when one or more bits of
STATUS1 register of ADC1 are
set.
0x1
R/W
12
ADC1_STATUS0
ADC1 STATUS0 Bit Mask. Set
this bit to enable an interrupt
when one or more bits of
STATUS0 register of ADC1 are
set.
0x1
R/W
11
ADC0_STATUS2
ADC0 STATUS2 Bit Mask. Set
this bit to enable an interrupt
when one or more bits of
STATUS2 register of ADC0 are
set.
0x1
R/W
10
ADC0_STATUS1
ADC0 STATUS1 Bit Mask. Set
this bit to enable an interrupt
when one or more bits of
STATUS1 register of ADC0 are
set.
0x1
R/W
9
ADC0_STATUS0
ADC0 STATUS0 Bit Mask. Set
this bit to enable an interrupt
when one or more bits of
STATUS0 register of ADC0 are
set.
0x1
R/W
8
DREADY_FREQ_ERROR
ADC Data Ready Frequency
Error Bit Mask. Set this bit to
enable an interrupt when ADC
Data Ready frequency is not
4KHz.
0x1
R/W
7
ERROR5
Error5 Bit Mask. Set this bit
to enable an interrupt when an
internal error occurs.
0x1
R/W
6
ADC_CRC_ERROR
ADC CRC Error Bit Mask. Set
this bit to enable an interrupt
when ADC CRC error occurs.
0x1
R/W
5
ERROR4
Error4 Bit Mask. Set this bit
to enable an interrupt when an
internal error occurs.
0x1
R/W
4
ERROR3
Error3 Bit Mask. Set this bit
to enable an interrupt when an
internal error occurs.
0x1
R/W
3
ERROR2
Error2 Bit Mask. Set this bit
to enable an interrupt when an
internal error occurs.
0x1
R/W
2
ERROR1
Error1 Bit Mask. Set this bit
to enable an interrupt when an
internal error occurs.
0x1
R/W
1
ERROR0
Error0 Bit Mask. Set this bit
to enable an interrupt when an
internal error occurs.
0x1
R/W



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