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CY8CKIT-059 数据表(PDF) 122 Page - Infineon Technologies AG |
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CY8CKIT-059 数据表(HTML) 122 Page - Infineon Technologies AG |
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122 / 140 page  Document Number: 001-84932 Rev. *N Page 121 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.8.3 Interrupt Controller 11.8.4 JTAG Interface Figure 11-79. JTAG Interface Timing Table 11-75. Interrupt Controller AC Specifications Parameter Description Conditions Min Typ Max Units Delay from interrupt signal input to ISR code execution from main line code[91] – – 12 Tcy CPU Delay from interrupt signal input to ISR code execution from ISR code (tail-chaining)[91] – – 6 Tcy CPU TDI TCK T_TDI_setup TDO (1/f_TCK) T_TDI_hold T_TDO_valid T_TDO_hold TMS T_TMS_setup T_TMS_hold Table 11-76. JTAG Interface AC Specifications[92] Parameter Description Conditions Min Typ Max Units f_TCK TCK frequency 3.3 V ≤ VDDD ≤ 5 V – – 12[93] MHz 1.71 V ≤ VDDD < 3.3 V – – 7[93] MHz T_TDI_setup TDI setup before TCK high (T/10) – 5 – – ns T_TMS_setup TMS setup before TCK high T/4 – – T_TDI_hold TDI, TMS hold after TCK high T = 1/f_TCK max T/4 – – T_TDO_valid TCK low to TDO valid T = 1/f_TCK max – – 2T/5 T_TDO_hold TDO hold after TCK high T = 1/f_TCK max T/4 – – T_nTRST Minimum nTRST pulse width f_TCK = 2 MHz 8 – – ns Notes 91. Arm Cortex-M3 NVIC spec. Visit www.arm.com for detailed documentation about the Cortex-M3 CPU. 92. Based on device characterization (Not production tested). 93. f_TCK must also be no more than 1/3 CPU clock frequency. |
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