CY8CKIT-059 datasheet(123/140 Pages) INFINEON

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Document Number: 001-84932 Rev. *N

Page 122 of 139

PSoC® 5LP: CY8C58LP Family

Datasheet

11.8.5 SWD Interface

Figure 11-80. SWD Interface Timing

11.8.6 TPIU Interface

SW DIO

(PSoC input)

SW DCK

T_SW DI_setup

SW DIO

(PSoC output)

(1/f_SW DCK)

T_SW DI_hold

T_SW DO_valid

T_SW DO_hold

Table 11-77. SWD Interface AC Specifications[94]

Parameter

Description

Conditions

Min

Typ

Max

Units

f_SWDCK

SWDCLK frequency

3.3 V

≤ VDDD ≤ 5 V

–

12[95]

MHz

1.71 V

≤ VDDD < 3.3 V

–

7[95]

MHz

1.71 V

≤ VDDD < 3.3 V, SWD over

USBIO pins

––

5.5[95]

MHz

T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max

T/4

–

T_SWDI_hold

SWDIO input hold after SWDCK high

T = 1/f_SWDCK max

T/4

–

T_SWDO_valid SWDCK high to SWDIO output

T = 1/f_SWDCK max

–

T/2

T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK max

––

Table 11-78. TPIU Interface AC Specifications[94]

Parameter

Description

Conditions

Min

Typ

Max

Units

TRACEPORT (TRACECLK) frequency

–

33[96]

MHz

SWV bit rate

–

33[96]

Mbit

Notes

94. Based on device characterization (Not production tested).

95. f_SWDCK must also be no more than 1/3 CPU clock frequency.

96. TRACEPORT signal frequency and bit rate are limited by GPIO output frequency, see Table 11-9 on page 77.

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