TMS320F2811 datasheet(110/173 Pages) TI

110 / 173 page

Electrical Specifications

110

April 2001 − Revised July 2007

SPRS174O

Table 6−13. STANDBY Mode Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td(IDLE-XCOH)

Delay time, IDLE instruction

executed to XCLKOUT high

32tc(SCO)

45tc(SCO) Cycles

Delay time, external wake

signal to program execution

resume†

− Wake-up from Flash

− Flash module in active

state

Without input

qualifier

12tc(CI) Cycles

td(WAKE-STBY)

− Wake-up from Flash

− Flash module in active

state

With input qualifier

12tc(CI) + tw(WAKE-INT) Cycles

td(WAKE-STBY)

− Wake-up from Flash

− Flash module in sleep state

Without input

qualifier

1125tc(SCO) Cycles

− Wake-up from Flash

− Flash module in sleep state

With input qualifier

1125tc(SCO) + tw(WAKE-INT) Cycles

− Wake-up from SARAM

Without input

qualifier

12tc(CI) Cycles

− Wake-up from SARAM

With input qualifier

12 tc(CI) + tw(WAKE-INT) Cycles

† This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the

wake-up) signal involves additional latency.

tw(WAKE-INT)

td(WAKE-STBY)

td(IDLE−XCOH)

32 SYSCLKOUT Cycles

Wake-up

Signal

X1/XCLKIN

XCLKOUT†

STANDBY

Normal Execution

STANDBY

Flushing Pipeline

Device

Status

NOTES: A. IDLE instruction is executed to put the device into STANDBY mode.

B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned

off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.

C. Clocks to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in

STANDBY mode.

D. The external wake-up signal is driven active (negative edge triggered shown as an example).

E. After a latency period, the STANDBY mode is exited.

F. Normal operation resumes. The device will respond to the interrupt (if enabled).

Figure 6−16. STANDBY Entry and Exit Timing

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