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TMS320F2811 数据表(PDF) 121 Page - Texas Instruments

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部件名 TMS320F2811
功能描述  Digital Signal Processors
PDF  173 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMS320F2811 数据表(HTML) 121 Page - Texas Instruments

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Electrical Specifications
120
April 2001 − Revised July 2007
SPRS174O
Data Valid
11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
1
7
6
10
3
2
SPISTE†
† In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active
between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6−27. SPI Master External Timing (Clock Phase = 1)



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