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TMS320F2811 数据表(PDF) 123 Page - Texas Instruments

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部件名 TMS320F2811
功能描述  Digital Signal Processors
PDF  173 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMS320F2811 数据表(HTML) 123 Page - Texas Instruments

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Electrical Specifications
122
April 2001 − Revised July 2007
SPRS174O
20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
16
14
13
12
SPISTE†
† In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain
low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6−28. SPI Slave Mode External Timing (Clock Phase = 0)



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