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TMS320F2811 数据表(PDF) 124 Page - Texas Instruments |
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TMS320F2811 数据表(HTML) 124 Page - Texas Instruments |
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124 / 173 page  Electrical Specifications 123 April 2001 − Revised July 2007 SPRS174O Table 6−27. SPI Slave Mode External Timing (Clock Phase = 1)†‡ NO. MIN MAX UNIT 12 tc(SPC)S Cycle time, SPICLK 8tc(LCO) ns 13§ tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S −10 0.5tc(SPC)S ns 13§ tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S −10 0.5tc(SPC)S ns 14§ tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S −10 0.5tc(SPC)S ns 14§ tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S −10 0.5tc(SPC)S ns 17§ tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S ns 17§ tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S ns 18§ tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity =0) 0.75tc(SPC)S ns 18§ tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity =1) 0.75tc(SPC)S ns 21§ tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 0 ns 21§ tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 0 ns 22§ tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)S ns 22§ tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)S ns † The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set. ‡ tc(SPC) = SPI clock cycle time = LSPCLK 4 or LSPCLK (SPIBRR ) 1) tc(LCO) = LSPCLK cycle time § The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit: 20 MHz MAX, master mode receive 12.5 MHz MAX Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX. |
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