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H8S/2214 数据表(PDF) 268 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 268 Page - Renesas Technology Corp |
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268 / 936 page  Section 7 DMA Controller Rev.4.00 Sep. 18, 2008 Page 208 of 872 REJ09B0189-0400 7.4.3 Module Stop Control Register A (MSTPCRA) Bit : 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : 0 0 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA7 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 17.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Bit 7—Module Stop (MSTP7): Specifies the DMAC module stop mode. Bits 7 MSTPA7 Description 0 DMAC module stop mode cleared (Initial value) 1 DMAC module stop mode set |
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