AM79C971VCW datasheet(188/265 Pages) AMD

188 / 265 page

188

Am79C971

ENP

End of Packet indicates that this

is the last buffer to be used by the

Am79C971

controller

for

this

frame. It is used for data chaining

buffers. If both STP and ENP are

set, the frame fits into one buffer

and there is no data chaining.

ENP is set by the host and is not

changed by the Am79C971 con-

troller.

BPE

Bus Parity Error is set by the

Am79C971 controller when a par-

ity error occurred on the bus inter-

face during a data transfers from

the transmit buffer associated

with

this

descriptor.

The

Am79C971 controller will only set

BPE when the advanced parity

error handling is enabled by set-

ting APERREN (BCR20, bit 10) to

1. BPE is set by the Am79C971

controller and cleared by the

host.

This bit does not exist, when the

Am79C971

controller

pro-

grammed to use 16-bit software

structures for the descriptor ring

entries (BCR20, bits 7-0, SW-

STYLE is cleared to 0).

22-16

RES

Reserved locations.

15-12

ONES

These four bits must be written as

ones. This field is written by the

host

and

unchanged

the

Am79C971 controller.

11-00

BCNT

Buffer Byte Count is the usable

length of the buffer pointed to by

this descriptor, expressed as the

two’s complement of the length of

the buffer. This is the number of

bytes from this buffer that will be

transmitted by the Am79C971

controller. This field is written by

the host and is not changed by

the Am79C971 controller. There

are no minimum buffer size re-

strictions.

TMD2

Bit

Name

Description

BUFF

Buffer

error

set

the

Am79C971

controller

during

transmission

when

the

Am79C971 controller does not

find the ENP flag in the current

descriptor and does not own the

next descriptor. This can occur in

either of two ways:

1. The OWN bit of the next buffer

is 0.

2. FIFO underflow occurred be-

fore the Am79C971 controller ob-

tained

the

STATUS

byte

(TMD1[31:24]) of the next de-

scriptor. BUFF is set by the

Am79C971

controller

and

cleared by the host.

If a Buffer Error occurs, an Un-

derflow Error will also occur.

BUFF is not valid when LCOL or

RTRY error is set during transmit

data chaining. BUFF is set by the

Am79C971

controller

and

cleared by the host.

UFLO

Underflow error indicates that the

transmitter has truncated a mes-

sage because it could not read

data from memory fast enough.

UFLO indicates that the FIFO has

emptied before the end of the

frame was reached.

When DXSUFLO (CSR3, bit 6) is

cleared to 0, the transmitter is

turned off when an UFLO error

occurs (CSR0, TXON = 0).

When DXSUFLO is set to 1, the

Am79C971 controller gracefully

recovers from an UFLO error. It

scans the transmit descriptor ring

until it finds the start of a new

frame and starts a new transmis-

sion.

UFLO is set by the Am79C971

controller and cleared by the

host.

EXDEF

Excessive Deferral. Indicates that

the transmitter has experienced

Excessive Deferral on this trans-

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