AM79C971VCW datasheet(57/265 Pages) AMD

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Am79C971

Figure 32.

32-Bit Software Model

If RXON is cleared to 0, the Am79C971 controller will

never poll RDTE locations.

In order to avoid missing frames, the system should

have at least one RDTE available. To minimize poll ac-

tivity, two RDTEs should be available. In this case, the

poll operation will only consist of the check of the status

of the current TDTE.

A typical transmit poll is the product of the following

conditions:

1. Am79C971 controller does not own the current

TDTE and TXDPOLL = 0 (CSR4, bit 12) and

TXON = 1 (CSR0, bit 4) and

the poll time has elapsed, or

2. Am79C971 controller does not own the current

TDTE and TXDPOLL = 0 and TXON = 1 and

a frame has just been received, or

3. Am79C971 controller does not own the current

TDTE and TXDPOLL = 0 and TXON = 1 and

a frame has just been transmitted.

Setting the TDMD bit of CSR0 will cause the microcode

controller to exit the poll counting code and immedi-

ately perform a polling operation. If RDTE ownership

has not been previously established, then an RDTE

poll will be performed ahead of the TDTE poll. If the mi-

crocode is not executing the poll counting code when

the TDMD bit is set, then the demanded poll of the

TDTE will be delayed until the microcode returns to the

poll counting code.

The user may change the poll time value from the de-

fault of 65,536 clock periods by modifying the value in

the Polling Interval register (CSR47).

Transmit Descriptor Table Entry

If, after a Transmit Descriptor Table Entry (TDTE) ac-

cess, the Am79C971 controller finds that the OWN bit

of that TDTE is not set, the Am79C971 controller re-

sumes the poll time count and re-examines the same

TDTE at the next expiration of the poll time count.

Initialization

Block

CSR1

CSR2

Rcv

Buff

RMD

Rcv Descriptor

Ring

•

1st

desc.

start

2nd

desc.

start

RMD

Xmt

Buff

TMD0

TMD1 TMD2 TMD3

Xmt Descriptor

Ring

•

1st

desc.

start

2nd

desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

PADR[31:0]

IADR[31:16]

IADR[15:0]

TLE RES RLE RES

MODE

PADR[47:32]

RES

LADRF[31:0]

LADRF[63:32]

RDRA[31:0]

TDRA[31:0]

20550D-35

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