AM79C971VCW datasheet(99/265 Pages) AMD

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Am79C971

disabling Magic Packet mode. Once either of these

events has occurred indicating that the system has de-

tected the assertion of INTA or an LED pin and is now

awake, the controller will continue polling the receive

and transmit descriptor rings where it left off. Re-initial-

ization should not be performed. If the part is re-initial-

ized, then the descriptor locations will be reset also,

and the Am79C971 controller will not start where it left

off.

If Magic Packet mode is disabled by the deassertion of

SLEEP, then in order to immediately re-enable Magic

Packet mode, the SLEEP pin must remain deasserted

for at least 200 ns before it is reasserted. If Magic

Packet mode is disabled by clearing MPEN, then it may

be immediately re-enabled by setting MPEN back to 1.

The PCI bus interface clock (CLK) is not required to be

running. Both INTA and the LED pins may be used to

indicate the receipt of a Magic Packet frame when the

CLK is stopped. If the system wishes to stop the CLK,

it should do so after enabling the Magic Packet mode.

The clock should be restarted before Magic Packet

mode is disabled if MPEN is being cleared, or the clock

must be restarted right after Magic Packet mode is dis-

abled if SLEEP is being deasserted. Otherwise, the re-

ceive FIFO may overflow if new frames arrive. The

network clock (XTAL) must continue running at all times

while in Magic Packet mode.

CAUTION: To prevent unwanted interrupts from other

active parts of the Am79C971 controller, care must be

taken to mask all likely interruptible events during

Magic Packet mode. An example would be the inter-

rupts from the MII which operate while in Magic Packet

mode.

IEEE 1149.1 (1990) Test Access Port

Interface

An IEEE 1149.1-compatible boundary scan Test Ac-

cess Port is provided for board-level continuity test and

diagnostics. All digital input, output, and input/output

pins are tested. Analog pins, including the AUI differen-

tial driver (DO

±) and receivers (DI±, CI±), and the crys-

tal input (XTAL1/XTAL2) pins are tested. The T-MAU

drivers TXD

±, TXP±, and receiver RXD± are also

tested. The following is a brief summary of the IEEE

1149.1-compatible test functions implemented in the

Am79C971 controller.

Boundary Scan Circuit

The boundary scan test circuit requires four pins (TCK,

TMS, TDI, and TDO), defined as the Test Access Port

(TAP). It includes a finite state machine (FSM), an

instruction register, a data register array, and a power-

on reset circuit. Internal pull-up resistors are provided

for the TDI, TCK, and TMS pins. The boundary scan

circuit remains active during Sleep mode.

TAP Finite State Machine

The TAP engine is a 16-state finite state machine

(FSM), driven by the Test Clock (TCK), and the Test

Mode Select (TMS) pins. An independent power-on

reset circuit is provided to ensure that the FSM is in the

TEST_LOGIC_RESET state at power-up. Therefore,

the TRST is not provided. The FSM is also reset when

TMS and TDI are high for five TCK periods.

Supported Instructions

In addition to the minimum IEEE 1149.1 requirements

(BYPASS, EXTEST, and SAMPLE instructions), three

additional instructions (IDCODE, TRIBYP, and SET-

BYP) are provided to further ease board-level testing.

All unused instruction codes are reserved. See Table

15 for a summary of supported instructions.

Instruction Register and Decoding Logic

After the TAP FSM is reset, the IDCODE instruction is

always invoked. The decoding logic gives signals to

control the data flow in the Data registers according to

the current instruction.

Boundary Scan Register

Each Boundary Scan Register (BSR) cell has two

stages. A flip-flop and a latch are used for the Serial

Shift Stage and the Parallel Output Stage, respectively.

There are four possible operation modes in the BSR

cell shown in Table 16.

Table 15.

IEEE 1149.1 Supported Instruction

Summary

Instruc-

tion

Name

Instruc-

tion

Code

Description

Mode

Selected

Data

EXTEST

0000

External Test Test

BSR

IDCODE

0001

ID Code

Inspection

Normal

ID REG

SAMPLE

0010

Sample

Boundary

Normal

BSR

TRIBYP

0011

Force Float

Normal

Bypass

SETBYP

0100

Control

Boundary To

1/0

Test

Bypass

BYPASS

1111

Bypass Scan Normal

Bypass

Table 16.

BSR Mode Of Operation

Capture

Shift

Update

System Function

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