AM79C971VCW datasheet(65/265 Pages) AMD

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Am79C971

first. The default value of DXMTFCS is 0 after

H_RESET.

ADD_FCS (TMD1, bit 29) allows the automatic gener-

ation and transmission of FCS on a frame-by-frame

basis. DXMTFCS should be set to 1 in this mode. To

generate FCS for a frame, ADD_FCS must be set in the

first descriptor of a frame (STP is set to 1). Note that bit

29 of TMD1 has the function of ADD_FCS if SWSTYLE

(BCR20, bits 7-0) is programmed to 0, 2, or 3.

Transmit Exception Conditions

Exception conditions for frame transmission fall into

two distinct categories: those conditions which are the

result of normal network operation, and those which

occur due to abnormal network and/or host related

events.

Normal events which may occur and which are handled

autonomously by the Am79C971 controller include col-

lisions within the slot time with automatic retry. The

Am79C971 controller will ensure that collisions which

occur within 512 bit times from the start of transmission

(including preamble) will be automatically retried with

no host intervention. The transmit FIFO ensures this by

guaranteeing that data contained within the FIFO will

not be overwritten until at least 64 bytes (512 bits) of

preamble plus address, length, and data fields have

been transmitted onto the network without encounter-

ing a collision. Note that if DRTY (CSR15, bit 5) is set

to 1 or if the network interface is operating in full-duplex

mode, no collision handling is required, and any byte of

frame data in the FIFO can be overwritten as soon as it

is transmitted.

If 16 total attempts (initial attempt plus 15 retries) fail,

the Am79C971 controller sets the RTRY bit in the cur-

rent transmit TDTE in host memory (TMD2), gives up

ownership (resets the OWN bit to 0) for this frame, and

processes the next frame in the transmit ring for trans-

mission.

Abnormal network conditions include:

s Loss of carrier

s Late collision

s SQE Test Error (Does not apply to 10BASE-T port

or 100-Mbps networks.)

These conditions should not occur on a correctly con-

figured IEEE 802.3 network operating in half-duplex

mode. If they do, they will be reported. None of these

conditions will occur on a network operating in full-

duplex mode. (See the section Full-Duplex Operation

for more detail.)

When an error occurs in the middle of a multi-buffer

frame transmission, the error status will be written in the

current descriptor. The OWN bit(s) in the subsequent

descriptor(s) will be cleared until the STP (the next

frame) is found.

Loss of Carrier

When operating in half-duplex mode, a loss of carrier

condition will be reported if the Am79C971 controller

cannot observe receive activity while it is transmitting

on the AUI or GPSI por t. In AUI mode, after the

Am79C971 controller initiates a transmission, it will ex-

pect to see data “looped-back” on the DI

± pair. This will

internally generate a “carrier sense,” indicating that the

integrity of the data path to and from the MAU is intact,

and that the MAU is operating correctly. This “carrier

sense” signal must be asserted before the last bit is

transmitted on DO

±. If “carrier sense” does not become

active in response to the data transmission, or be-

comes inactive before the end of transmission, the loss

of carrier (LCAR) error bit will be set in TMD2 after the

frame has been transmitted. The frame will not be re-

tried on the basis of an LCAR error. In GPSI mode,

LCAR will be asserted if RXEN does not go active dur-

ing the transmission.

When the internal 10BASE-T port is selected, LCAR

will be reported for every frame transmitted while the

network interface is in the Link Fail state.

Late Collision

A late collision will be reported if a collision condition

occurs after one slot time (512 bit times) after the trans-

mit process was initiated (first bit of preamble com-

menced). The Am79C971 controller will abandon the

transmit process for that frame, set Late Collision

(LCOL) in the associated TMD2, and process the next

transmit frame in the ring. Frames experiencing a late

collision will not be retried. Recovery from this condi-

tion must be performed by upper layer software.

SQE Test Error

During the IPG time following the completion of a trans-

mitted message, the AUI CI

± pair is asserted by some

transceivers as a self-test. The integral MENDEC will

expect the SQE Test Message (nominal 10-MHz se-

quence) to be returned via the CI

± pair within a 40-net-

work bit-time period after DI

± goes inactive (this does

not apply if the 10BASE-T port is selected). If the CI

input is not asserted within the 40 network bit-time pe-

riod following the completion of transmission, then the

Am79C971 controller will set the CERR bit in CSR0. In

GPSI mode, CLSN must be asserted after the trans-

mission or otherwise CERR will be set. CERR will be

asserted in 10BASE-T mode, or in the 10BASE-T

mode through the MII after transmit, if the network port

is in Link Fail state. CERR will never cause INTA to be

activated. It will, however, set the ERR bit CSR0.

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