AM79C971VCW datasheet(62/265 Pages) AMD

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Am79C971

Medium Allocation

The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990)

requires that the CSMA/CD MAC monitor the medium

for traffic by watching for carrier activity. When carrier is

detected, the media is considered busy, and the MAC

should defer to the existing message.

The ISO 8802-3 (IEEE/ANSI 802.3) standard also al-

lows optionally a two-part deferral after a receive mes-

sage.

See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:

Note: It is possible for the PLS carrier sense indication

to fail to be asserted during a collision on the media. If

the deference process simply times the inter-Frame

gap based on this indication, it is possible for a short in-

terFrame gap to be generated, leading to a potential re-

ception failure of a subsequent frame. To enhance

system robustness, the following optional measures,

as specified in 4.2.8, are recommended when Inter-

Frame-SpacingPart1 is other than 0:

1. Upon completing a transmission, start timing the in-

terrupted gap, as soon as transmitting and carrier

sense are both false.

2. When timing an inter-frame gap following reception,

reset the inter-frame gap timing if carrier sense be-

comes true during the first 2/3 of the inter-frame gap

timing interval. During the final 1/3 of the interval,

the timer shall not be reset to ensure fair access to

the medium. An initial period shorter than 2/3 of the

interval is permissible including 0.

The MAC engine implements the optional receive two

part deferral algorithm, with an InterFrameSpacing-

Part1 time of 6.0

µs. The InterFrameSpacingPart 2 in-

terval is, therefore, 3.4

µs.

The Am79C971 controller will perform the two-part

deferral algorithm as specified in Section 4.2.8 (Pro-

cess Deference). The Inter Packet Gap (IPG) timer will

start timing the 9.6

µs InterFrameSpacing after the re-

ceive carrier is deasserted. During the first part deferral

(InterFrameSpacingPart1 - IFS1), the Am79C971 con-

troller will defer any pending transmit frame and re-

spond to the receive message. The IPG counter will be

cleared to 0 continuously until the carrier deasserts, at

which point the IPG counter will resume the 9.6

µs

count once again. Once the IFS1 period of 6.0

µs has

elapsed, the Am79C971 controller will begin timing the

second part deferral (InterFrameSpacingPart2 - IFS2)

of 3.4

µs. Once IFS1 has completed and IFS2 has com-

menced, the Am79C971 controller will not defer to a re-

ceive frame if a transmit frame is pending. This means

that the Am79C971 controller will not attempt to receive

the receive frame, since it will start to transmit and gen-

erate a collision at 9.6

µs. The Am79C971 controller

will complete the preamble (64-bit) and jam (32-bit) se-

quence before ceasing transmission and invoking the

random backoff algorithm.

The Am79C971 controller allows the user to program

the IPG and the first par t deferral (InterFrame-

SpacingPart1 - IFS1) through CSR125. By changing

the IPG default value of 96 bit times (60h), the user can

ad just t he fa ir n e ss or a g g r essivene s s of the

Am79C971 MAC on the network. By programming a

lower number of bit times than the ISO/IEC 8802-3

standard requires, the Am79C971 MAC engine will be-

come more aggressive on the network. This aggressive

nature will give rise to the Am79C971 controller possi-

bly capturing the network at times by forcing other less

aggressive compliant nodes to defer. By programming

a larger number of bit times, the Am79C971 MAC will

become less aggressive on the network and may defer

more often than normal. The performance of the

Am79C971 controller may decrease as the IPG value

is increased from the default value, but the resulting be-

havior may improve network performance by reducing

collisions. The Am79C971 controller uses the same

IPG for back-to-back transmits and receive-to-transmit

accesses. Changing IFS1 will alter the period for which

the Am79C971 MAC engine will defer to incoming re-

ceive frames.

CAUTION: Care must be exercised when altering

these parameters. Adverse network activity could

result!

This transmit two-part deferral algorithm is imple-

mented as an option which can be disabled using the

DXMT2PD bit in CSR3. The IFS1 programming will

have no effect when DXMT2PD is set to 1, but the IPG

programming value is still valid. Two part deferral after

transmission is useful for ensuring that severe IPG

shrinkage cannot occur in specific circumstances,

causing a transmit message to follow a receive mes-

sage so closely as to make them indistinguishable.

During the time period immediately after a transmission

has been completed, the external transceiver (in the

case of a standard AUI connected device) should gen-

erate the SQE Test message (a nominal 10-MHz burst

of 5 to 15 bit times duration) on the CI

± pair (within 0.6

to 1.6

µs after the transmission ceases). During the

time period in which the SQE Test message is ex-

pected, the Am79C971 controller will not respond to re-

ceive carrier sense.

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