AM79C971VCW datasheet(78/265 Pages) AMD

78 / 265 page

Am79C971

The MII Management Interface has a built-in detection

system to allow the Am79C971 controller to determine

if an external PHY is attached. The MDIO I/O pin has a

resistor network between the Am79C971 controller and

the external PHY that will assert a static 1 when

connected. If there is no external PHY connected, the

resistor network will drive a static zero. This information

is signaled by the interrupt MPDTINT (CSR7, MIIPDTI,

bit 1), and the status is provided by reading the Media

Independent Interface PHY Detected (MIIPD) (BCR32,

bit 14). This resistor network is only required on an

exposed MII connector.

MII Management Frames

MII management frames are automatically generated

by the Am79C971 controller and conform to the MII

clause in the IEEE 802.3u standard.

The start of the frame is a preamble of 32 ones and

guarantees that all of the external PHYs are synchro-

nized on the same interface. (See Figure 39.) Loss of

synchronization is possible due to the hot-plugging ca-

pability of the exposed MII.

The IEEE 802.3 specification allows you to drop the

preamble, if after reading the MII Status Register from

the external PHY you can determine that the external

PHY will support Preamble Suppression (BCR34, bit

6). After having a valid MII Status Register read, the

Am79C971 controller will then drop the creation of the

preamble stream until a reset occurs, receives a read

error, or the external PHY is disconnected.

Figure 39.

Frame Format at the MII Interface Connection

This is followed by a start field (ST) and an operation

field (OP). The operation field (OP) indicates whether

the Am79C971 controller is initiating a read or write op-

eration. This is followed by the external PHY address

(PHYAD) and the register address (REGAD) pro-

grammed in BCR33. The internal PHYAD is at location

1Fh and the internal register address space REGAD is

00h - 08h. The external PHY may have a larger ad-

dress space starting at 10h - 1Fh. This is the address

range set aside by the IEEE as vendor usable address

space and will vary from vendor to vendor. This field is

followed by a bus turnaround field. During a read oper-

ation, the bus turnaround field is used to determine if

the external PHY is responding correctly to the read re-

quest or not. The Am79C971 controller will tri-state the

MDIO for both MDC cycles. During the second cycle, if

the external PHY is synchronized to the Am79C971

controller, the external PHY will drive a 0. If the external

PHY does not drive a 0, the Am79C971 controller will

signal a MREINT (CSR7, bit 9) interrupt, if MREINTE

(CSR7, bit 8) is set to a 1, indicating the Am79C971

controller had an MII management frame read error

and that the data in BCR34 is not valid. The data field

to/from the internal or external PHY is read or written

into the BCR34 register. The last field is an IDLE field

that is necessary to give ample time for drivers to turn

off before the next access. The Am79C971 controller

will drive the MDC to 0 and tri-state the MDIO anytime

the MII Management Port is not active.

To help to speed up the reading and writing of the MII

management frames to the external PHY, the MDC can

be sped up to 10 MHz by setting the FMDC bits in

BCR32. The IEEE 802.3 specification requires use of

the 2.5-MHz clock rate, but 5 MHz and 10 MHz are

available for the user. The intended applications are

that the 10-MHz clock rate can be used for a single ex-

ternal PHY on an adapter card or motherboard. The 5-

MHz clock rate can be used for an exposed MII with

one external PHY attached. The 2.5-MHz clock rate is

intended to be used when multiple external PHYs are

connected to the MII Management Port or if compli-

ance to the IEEE 802.3u standard is required.

Auto-Poll External PHY Status Polling

As defined in the IEEE 802.3 standard, the external

PHY attached to the Am79C971 controller’s MII has no

way of communicating important timely status informa-

tion back to Am79C971 controller. The Am79C971

controller has no way of knowing that an external PHY

has undergone a change in status without polling the

MII status register. To prevent problems from occurring

with i nadequate ho st or softwar e po lling, the

Am79C971 controller will Auto-Poll when APEP

(BCR32, bit 11) is set to 1 to insure that the most cur-

rent information is available. See Appendix E, Auto Ne-

Preamb le

1111....1111

10 Rd

01 Wr

PHY

Address

Z0 Rd

10 Wr

Data

Idle

Bits

miiframe

Bits

Bit

20550D-42

AM79C971VCW 数据表(PDF) 78 Page - Advanced Micro Devices

AM79C971VCW 数据表(HTML) 78 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载