AM79C971VCW datasheet(19/265 Pages) AMD

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Am79C971

INTA

Interrupt Request

Output

An attention signal which indicates that one or more of

the following status flags is set: BABL, EXDINT, IDON,

JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT,

SINT, SLPINT, TINT, TXSTRT, UINT, MCCIINT, MC-

CINT, MPDTINT, MAPINT, MREINT, and STINT. Each

status flag has either a mask or an enable bit which al-

lows for suppression of INTA assertion. Table 1 shows

the flag meanings.

By default INTA is an open-drain output. For applica-

tions that need a high-active edge-sensitive interrupt

signal, the INTA pin can be configured for this mode by

setting INTLEVEL (BCR2, bit 7) to 1.

When RST is active, INTA is the output for NAND tree

testing.

IRDY

Initiator Ready

Input/Output

IRDY indicates the ability of the initiator of the transac-

tion to complete the current data phase. IRDY is used

in conjunction with TRDY. Wait states are inserted until

both IRDY and TRDY are asserted simultaneously. A

data phase is completed on any clock when both IRDY

and TRDY are asserted.

When the Am79C971 controller is a bus master, it as-

serts IRDY during all write data phases to indicate that

valid data is present on AD[31:0]. During all read data

phases, the device asserts IRDY to indicate that it is

ready to accept the data.

When the Am79C971 controller is the target of a trans-

action, it checks IRDY during all write data phases to

determine if valid data is present on AD[31:0]. During

all read data phases, the device checks IRDY to deter-

mine if the initiator is ready to accept the data.

When RST is active, IRDY is an input for NAND tree

testing.

PAR

Parity

Input/Output

Parity is even parity across AD[31:0] and C/BE[3:0].

When the Am79C971 controller is a bus master, it gen-

erates parity during the address and write data phases.

It checks parity during read data phases. When the

Am79C971 controller operates in slave mode, it checks

parity during every address phase. When it is the target

of a cycle, it checks parity during write data phases and

it generates parity during read data phases.

When RST is active, PAR is an input for NAND tree

testing.

Table 1.

Interrupt Flags

Name

Description

Mask Bit

Interrupt Bit

BABL

Babble

CSR3, bit 14

CSR0, bit 14

EXDINT

Excessive

Deferral

CSR5, bit 6

CSR5, bit 7

IDON

Initialization

Done

CSR3, bit 8

CSR0, bit 8

JAB

Jabber

CSR4, bit 0

CSR4, bit 1

MERR

Memory Error

CSR3, bit 11

CSR0, bit 11

MISS

Missed Frame

CSR3, bit 12

CSR0, bit 12

MFCO

Missed Frame

Count Over-

flow

CSR4, bit 8

CSR4, bit 9

MPINT

Magic Packet

Interrupt

CSR5, bit 3

CSR5, bit 4

RCVCCO

Receive

Collision Count

Overflow

CSR4, bit 4

CSR4, bit 5

RINT

Receive

Interrupt

CSR3, bit 10

CSR0, bit 10

SLPINT

Sleep Interrupt CSR5, bit 8

CSR5, bit 9

SINT

System Error

CSR5, bit 10

CSR5, bit 11

TINT

Transmit

Interrupt

CSR3, bit 9

CSR0, bit 9

TXSTRT

Transmit Start

CSR4, bit 2

CSR4, bit 3

UINT

User Interrupt

CSR4, bit 7

CSR4, bit 6

MCCIINT

Internal MII

Management

Command

Complete

Interrupt

CSR7, bit 2

CSR7, bit 3

MCCINT

MII

Management

Command

Complete

Interrupt

CSR7, bit 4

CSR7, bit 5

MPDTINT

MII PHY Detect

Transition

Interrupt

CSR7, bit 0

CSR7, bit 1

Name

Description

Mask Bit

Interrupt Bit

MAPINT

MII Auto-Poll

Interrupt

CSR7, bit 6

CSR7, bit 7

MREINT

MII

Management

Frame Read

Error Interrupt

CSR7, bit 8

CSR7, bit 9

STINT

Software Timer

Interrupt

CSR7, bit 10

CSR7, bit 11

Table 1.

Interrupt Flags

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