AM79C971VCW datasheet(92/265 Pages) AMD

92 / 265 page

Am79C971

No SRAM Configuration

If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the

SRAM size register, the Am79C971 controller will as-

sume that there is no SRAM present and will reconfig-

ure the four internal FIFOs into two FIFOs, one for

transmit and one for receive. The FIFOs will operate

the same as in the PCnet-PCI II controller. When the

SRAM SIZE (BCR25, bits 7-0) value is 0, the SRAM

BND (BCR26, bits 7-0) are ignored by the Am79C971

controller. See Figure 50.

NOTE: A “No SRAM configuration” is only valid for

10Mb mode. In 100Mb mode, SRAM is mandatory and

must always be used.

Low Latency Receive Configuration

If the LOLATRX (BCR27, bit 4) bit is set to 1, then the

Am79C971 controller will configure itself for a low la-

tency receive configuration. In this mode, external

SRAM is required at all times. If the SRAM_SIZE

(BCR25, bits 7-0) value is 0, the Am79C971 controller

will not configure for low latency receive mode. The

Am79C971 controller will provide a fast path on the re-

ceive side bypassing the external RAM. All transmit

traffic will go to the SRAM, so SRAM_BND (BCR26,

bits 7-0) has no meaning in low latency receive mode.

When the Am79C971 controller has received 16 bytes

from the network, it will start a DMA request to the PCI

Bus Interface Unit. The Am79C971 controller will not

wait for the first 64 bytes to pass to check for collisions

in Low Latency Receive mode. The Am79C971 control-

ler must be in STOP before switching to this mode. See

Figure 51.

CAUTION: To provide data integrity when switching

into and out of the low latency mode, DO NOT SET

the FASTSPNDE bit when setting the SPND bit. Re-

c e i ve f r am es WI L L be ov e r w r i tte n a nd th e

Am79C971 controller may give erratic behavior

when it is enabled again.

Direct SRAM Access

The SRAM can be accessed through the Expansion

Bus Data port (BCR30). To access this data port, the

user must load the upper address EPADDRU (BCR29,

bits 3-0) and set FLASH (BCR29, bit 15) to 0. Then the

user will load the lower 16 bits of address EPADDRL

(BCR28, bits 15-0). To initiate a read, the user reads

the Expansion Bus Data Port (BCR30). This slave ac-

cess from the PCI will result in a retry for the very first

access. Subsequent accesses may give a retry or not,

depending on whether or not the data is present and

valid. The direct SRAM access uses the same FLASH/

EPROM access except for accessing the SRAM in

word format instead of byte format. This access is

meant to be a diagnostic access only. The SRAM can

only be accessed while the Am79C971 controller is in

STOP or SPND (FASTSPNDE is set to 0) mode.

Figure 50.

Block Diagram No SRAM Configuration

PCI Bus

Interface

Unit

802.3

MAC

Core

Bus

Rcv

FIFO

MAC

Rcv

FIFO

Bus

Xmt

FIFO

MAC

Xmt

FIFO

Buffer

Management

Unit

FIFO

Control

20550D-53

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