AM79C971VCW datasheet(34/265 Pages) AMD

34 / 265 page

Am79C971

During the boot procedure, the system will try to find an

Expansion ROM. A PCI system assumes that an Ex-

pansion ROM is present when it reads the ROM signa-

ture 55H (byte 0) and AAH (byte 1). A design without

Expansion ROM can guarantee that the Expansion

ROM detection fails by connecting two adjacent EBD

pins together.

Slave Cycle Termination

There are three scenarios besides normal completion

of a transaction where the Am79C971controller is the

target of a slave cycle and it will terminate the access.

Disconnect When Busy

The Am79C971controller cannot service any slave ac-

cess while it is reading the contents of the EEPROM.

Simultaneous access is not possible to avoid conflicts,

since the EEPROM is used to initialize some of the PCI

configuration space locations and most of the BCRs.

The EEPROM read operation will always happen auto-

matically after the deassertion of the RST pin. In addi-

tion, the host can start the read operation by setting the

PREAD bit (BCR19, bit 14). While the EEPROM read

is on-going, the Am79C971controller will disconnect

any slave access where it is the target by asserting

STOP together with DEVSEL, while driving TRDY high.

STOP will stay asserted until the end of the cycle.

Note that I/O and memory slave accesses will only be

disconnected if they are enabled by setting the IOEN or

MEMEN bit in the PCI Command register. Without the

enable bit set, the cycles will not be claimed at all.

Since H_RESET clears the IOEN and MEMEN bits for

the automatic EEPROM read after H_RESET, the dis-

connect only applies to configuration cycles.

A second situation where the Am79C971controller will

generate a PCI disconnect/retry cycle is when the host

tries to access any of the I/O resources right after hav-

ing read the Reset register. Since the access gener-

ates an internal reset pulse of about 1

µs in length, all

further slave accesses will be deferred until the internal

reset operation is completed. See Figure 6.

Disconnect Of Burst Transfer

The Am79C971controller does not support burst ac-

cess to the configuration space, the I/O resources, or to

the Expansion Bus. The host indicates a burst transac-

tion by keeping FRAME asserted during the data

phase. When the Am79C971controller sees FRAME

and IRDY asserted in the clock cycle before it wants to

assert TRDY, it also asserts STOP at the same time.

The transfer of the first data phase is still successful,

since IRDY and TRDY are both asserted. See Figure 7.

Figure 6.

Disconnect Of Slave Cycle When Busy

Figure 7.

Disconnect Of Slave Burst Transfer - No

Host Wait States

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

2345

CMD

PAR

DATA

ADDR

20550D-9

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

2345

CMD

PAR

DATA

ADDR

20550D-10

AM79C971VCW 数据表(PDF) 34 Page - Advanced Micro Devices

AM79C971VCW 数据表(HTML) 34 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载