AM79C971VCW datasheet(58/265 Pages) AMD

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Am79C971

If the OWN bit of the TDTE is set, but the Start of

Packet (STP) bit is not set, the Am79C971 controller

will immediately request the bus in order to clear the

OWN bit of this descriptor. (This condition would nor-

mally be found following a late collision (LCOL) or retry

(RTRY) error that occurred in the middle of a transmit

frame chain of buffers.) After resetting the OWN bit of

this descriptor, the Am79C971 controller will again im-

mediately request the bus in order to access the next

TDTE location in the ring.

If the OWN bit is set and the buffer length is 0, the OWN

bit will be cleared. In the C-LANCE device, the buffer

length of 0 is interpreted as a 4096-byte buffer. A zero

length buffer is acceptable as long as it is not the last

buffer in a chain (STP = 0 and ENP = 1).

If the OWN bit and STP are set, then microcode control

proceeds to a routine that will enable transmit data

transfers to the FIFO. The Am79C971 controller will

look ahead to the next transmit descriptor after it has

performed at least one transmit data transfer from the

first buffer.

If the Am79C971 controller does not own the next

TDTE (i.e., the second TDTE for this frame), it will com-

plete transmission of the current buffer and update the

status of the current (first) TDTE with the BUFF and

UFLO bits being set. If DXSUFLO (CSR3, bit 6) is

cleared to 0, the underflow error will cause the transmit-

ter to be disabled (CSR0, TXON = 0). The Am79C971

controller will have to be re-initialized to restore the

transmit function. Setting DXSUFLO to 1 enables the

Am79C971 controller to gracefully recover from an un-

derflow error. The device will scan the transmit descrip-

tor ring until it finds either the start of a new frame or a

TDTE it does not own. To avoid an underflow situation

in a chained buffer transmission, the system should al-

ways set the transmit chain descriptor own bits in re-

verse order.

If the Am79C971 controller does own the second TDTE

in a chain, it will gradually empty the contents of the first

buffer (as the bytes are needed by the transmit opera-

tion), perform a single-cycle DMA transfer to update the

status of the first descriptor (clear the OWN bit in

TMD1), and then it may perform one data DMA access

on the second buffer in the chain before executing an-

other

lookahead operation. (i.e., a lookahead to the

third descriptor.)

It is imperative that the host system never reads the

TDTE OWN bits out of order. The Am79C971 controller

normally clears OWN bits in strict FIFO order. However,

the Am79C971 controller can queue up to two frames

in the transmit FIFO. When the second frame uses

buffer chaining, the Am79C971 controller might return

ownership out of normal FIFO order. The OWN bit for

last (and maybe only) buffer of the first frame is not

cleared until transmission is completed. During the

transmission the Am79C971 controller will read in buff-

ers for the next frame and clear their OWN bits for all

but the last one. The first and all intermediate buffers of

the second frame can have their OWN bits cleared be-

fore the Am79C971 controller returns ownership for the

last buffer of the first frame.

If an error occurs in the transmission before all of the

bytes of the current buffer have been transferred, trans-

mit status of the current buffer will be immediately up-

dated. If the buffer does not contain the end of packet,

the Am79C971 controller will skip over the rest of the

frame which experienced the error. This is done by re-

turning to the polling microcode where the Am79C971

controller will clear the OWN bit for all descriptors with

OWN = 1 and STP = 0 and continue in like manner until

a descriptor with OWN = 0 (no more transmit frames in

the ring) or OWN = 1 and STP = 1 (the first buffer of a

new frame) is reached.

At the end of any transmit operation, whether success-

ful or with errors, immediately following the completion

of the descriptor updates, the Am79C971 controller will

always perform another polling operation. As described

earlier, this polling operation will begin with a check of

the current RDTE, unless the Am79C971 controller al-

ready owns that descriptor. Then the Am79C971 con-

troller will poll the next TDTE. If the transmit descriptor

OWN bit has a 0 value, the Am79C971 controller will

resume incrementing the poll time counter. If the trans-

mit descriptor OWN bit has a value of 1, the Am79C971

controller will begin filling the FIFO with transmit data

and initiate a transmission. This end-of-operation poll

coupled with the TDTE lookahead operation allows the

Am79C971 controller to avoid inserting poll time counts

between successive transmit frames.

By default, whenever the Am79C971 controller com-

pletes a transmit frame (either with or without error) and

writes the status information to the current descriptor,

then the TINT bit of CSR0 is set to indicate the comple-

tion of a transmission. This causes an interrupt signal if

the IENA bit of CSR0 has been set and the TINTM bit

of CSR3 is cleared. The Am79C971 controller provides

two modes to reduce the number of transmit interrupts.

The interrupt of a successfully transmitted frame can

be suppressed by setting TINTOKD (CSR5, bit 15) to

1. Another mode, which is enabled by setting LTINTEN

(CSR5, bit 14) to 1, allows suppression of interrupts for

successful transmissions for all but the last frame in a

sequence.

Receive Descriptor Table Entry

If the Am79C971 controller does not own both the cur-

rent and the next Receive Descriptor Table Entry

(RDTE), then the Am79C971 controller will continue to

poll according to the polling sequence described

above. If the receive descriptor ring length is one, then

there is no next descriptor to be polled.

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