AM79C971VCW datasheet(22/265 Pages) AMD

22 / 265 page

Am79C971

not used,

±10% accuracy is sufficient for the clock

source.

Note: When the Am79C971 controller is in coma

mode, there is an internal 22 k

Ω resistor from XTAL1 to

ground. If an external source drives XTAL1, some

power consumption will be consumed driving this resis-

tor. If XTAL1 is driven LOW at this time, power con-

sumption will be minimized. In this case, XTAL1 must

remain active for at least 30 cycles after the assertion

of SLEEP and deassertion of REQ.

XTAL2

Crystal Oscillator Out

Output

The internal clock generator uses a 20-MHz crystal that

is attached to the pins XTAL1 and XTAL2. The network

data rate is one-half of the crystal frequency. If an ex-

ternal clock source is used on XTAL1, then XTAL2

should be left unconnected.

EEPROM Interface

EECS

EEPROM Chip Select

Output

This pin is designed to directly interface to a serial EE-

PROM that uses the 93C46 EEPROM interface proto-

col. EECS is connected to the EEPROM’s chip select

pin. It is controlled by either the Am79C971 controller

during command portions of a read of the entire EE-

PROM, or indirectly by the host system by writing to

BCR19, bit 2.

When RST is active, EECS is an input for NAND tree

testing.

EEDI

EEPROM Data In

Output

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EEDI is connected to the EEPROM’s data input

pin. It is controlled by either the Am79C971 controller

during command portions of a read of the entire

EEPROM, or indirectly by the host system by writing to

BCR19, bit 0.

Note: The EEDI pin is multiplexed with the LED0 pin.

When RST is active, EEDI is an input for NAND tree

testing.

EEDO

EEPROM Data Out

Input

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EEDO is connected to the EEPROM’s data out-

put pin. It is controlled by either the Am79C971

controller during command portions of a read of the en-

tire EEPROM, or indirectly by the host system by read-

ing from BCR19, bit 0.

Note: The EEDO pin is multiplexed with the LED3,

MIIRXFRTGD, and SRD pins.

When RST is active, EEDO is an input for NAND tree

testing.

EESK

EEPROM Serial clock

Input/Output

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EESK is connected to the EEPROM’s clock pin.

It is controlled by either the Am79C971 controller di-

rectly during a read of the entire EEPROM, or indirectly

by the host system by writing to BCR19, bit 1.

Note: The EESK pin is multiplexed with the LED1 and

SFBD pins.

The EESK pin is also used during EEPROM Auto-

Detection to determine whether or not an EEPROM is

present at the Am79C971 controller interface. At the

rising edge of the last CLK edge while RST is asserted,

EESK is sampled to determine the value of the EEDET

bit in BCR19. A sampled HIGH value means that an

EEPROM is present, and EEDET will be set to 1. A

sampled LOW value means that an EEPROM is not

present, and EEDET will be set to 0. See the EEPROM

Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull

up or pull down resistor must be attached instead to re-

solve the EEDET setting.

When RST is active, EESK is an input for NAND tree

testing.

WARNING: The input signal level of EESK must be

valid for correct EEPROM detection before the

deassertion of RST.

Expansion Bus Interface

EBUA_EBA[7:0]

Expansion Bus Upper Address/

Expansion Bus Address [7:0]

Output

The EBUA_EBA[7:0] pins provide the least and most

significant bytes of address on the Expansion Bus. The

most significant address byte (address bits [15:8] dur-

ing SRAM accesses; address bits [19:16] during boot

device accesses) is valid on these pins at the beginning

of an SRAM or boot device access, at the rising edge

of AS_EBOE. This upper address byte must be stored

externally in a D flip-flop. During subsequent cycles of

an SRAM or boot device access, address bits [7:0] are

present on these pins.

All EBUA_EBA[7:0] outputs are forced to a constant

level to conserve power while no access on the Expan-

sion Bus is being performed.

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