AM79C971VCW datasheet(82/265 Pages) AMD

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Am79C971

The SFBD signal will initially be LOW. The assertion of

SFBD is a signal to the external address detection logic

that the SFD has been detected and that subsequent

SRDCLK cycles will deliver packet data to the external

logic. Therefore, when SFBD is asserted, the external

address matching logic should begin de-serialization of

the SRD data and send the resulting destination ad-

dress to a Content Addressable Memory (CAM) or

other address detection device. In order to reduce the

amount of logic external to the Am79C971 controller for

multiple address decoding systems, the SFBD signal

will toggle at each new byte boundary within the

packet, subsequent to the SFD. This eliminates the

need for externally supplying byte framing logic.

SRD is the decoded NRZ data from the network. This

signal can be used for external address detection. Note

that when the 10BASE-T port is selected, transitions on

SRD will only occur during receive activity. When the

AUI or GPSI port is selected, transitions on SRD will

occur during receive activity.

The EAR pin should be driven LOW by the external ad-

dress comparison logic to reject a frame.

If an address match is detected by comparison with ei-

ther the Physical Address or Logical Address Filter reg-

isters contained within the Am79C971 controller or the

frame is of the type ’Broadcast’, then the frame will be

accepted regardless of the condition of EAR. When the

EADISEL bit of BCR2 is set to 1 and the Am79C971

controller is programmed to promiscuous mode

(PROM bit of the Mode Register is set to 1), then all in-

coming frames will be accepted, regardless of any ac-

tivity on the EAR pin.

Internal address match is disabled when PROM

(CSR15, bit 15) is cleared to 0, DRCVBC (CSR15, bit

14) and DRCVPA (CSR15, bit 13) are set to 1, and the

Logical Address Filter registers (CSR8 to CSR11) are

programmed to all zeros.

When the EADISEL bit of BCR2 is set to 1 and internal

address match is disabled, then all incoming frames

will be accepted by the Am79C971 controller, unless

the EAR pin becomes active during the first 64 bytes of

the frame (excluding preamble and SFD). This allows

external address lookup logic approximately 58 byte

times after the last destination address bit is available

to generate the EAR signal, assuming that the

Am79C971 controller is not configured to accept runt

packets. The EADI logic only samples EAR from 2 bit

times after SFD until 512 bit times (64 bytes) after SFD.

The frame will be accepted if EAR has not been as-

serted during this window. If Runt Packet Accept

(CSR124, bit 3) is enabled, then the EAR signal must

be generated prior to the 8 bytes received, if frame re-

jection is to be guaranteed. Runt packet sizes could be

as short as 12 byte times (assuming 6 bytes for source

address, 2 bytes for length, no data, 4 bytes for FCS)

after the last bit of the destination address is available.

EAR must have a pulse width of at least 110 ns.

The EADI outputs continue to provide data throughout

the reception of a frame. This allows the external logic

to capture frame header information to determine pro-

tocol type, internetworking information, and other use-

ful data.

The EADI interface will operate as long as the STRT bit

in CSR0 is set, even if the receiver and/or transmitter

are disabled by software (DTX and DRX bits in CSR15

are set). This configuration is useful as a semi-power-

down mode in that the Am79C971 controller will not

perform any power-consuming DMA operations. How-

ever, external circuitry can still respond to control

frames on the network to facilitate remote node control.

Table 11 summarizes the operation of the EADI inter-

face.

External Address Detection Interface: External

PHY

When using the MII, the EADI interface changes to re-

flect the changes on that interface. Except for the nota-

tions below the interface conforms to the previous

functionality. The data arrives in nibbles and can be at

a rate of 25 MHz or 2.5 MHz.

The MII provides all necessary data and clock signals

needed for the EADI interface. Consequently, SRDCLK

and SRD are not used and are driven to 0. Data for the

EADI is the RXD(3:0) receive data provided to the MII.

Instead of deserializing the network data, the user will

receive the data as 4 bit nibbles. RX_CLK is provided

to allow clocking of the RXD(3:0) receive nibble stream

into the external address detection logic. The RXD(3:0)

data is synchronous to the rising edge of the RX_CLK.

The assertion of SFBD is a signal to the external ad-

dress detection logic that the SFD has been detected

and that the first valid data nibble is on the RXD(3:0)

data bus. The SFBD signal is delayed one RX_CLK

cycle from the above definition and actually signals the

start of valid data. In order to reduce the amount of

logic external to the Am79C971 controller for multiple

Table 11.

EADI Operations

PROM

EAR

Required

Timing

Received

Messages

No timing

requirements

All received frames

No timing

requirements

All received frames

Low for 110 ns

during the window

from 0 bits after

SFD to 512 bits

after SFD

Am79C971

controller internal

physical address

and logical address

filter matches and

broadcast frames

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