AM79C971VCW datasheet(97/265 Pages) AMD

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Am79C971

There are two checksum locations within the EE-

PROM. The first checksum will be used by AMD driver

software to verify that the ISO 8802-3 (IEEE/ANSI

802.3) station address has not been corrupted. The

value of bytes 0Ch and 0Dh should match the sum of

bytes 00h through 0Bh and 0Eh and 0Fh. The second

checksum location (byte 3Fh) is not a checksum total,

but is, instead, a checksum adjustment. The value of

this byte should be such that the total checksum for the

entire 64 bytes of EEPROM data equals the value FFh.

The checksum adjust byte is needed by the Am79C971

controller in order to verify that the EEPROM content

has not been corrupted.

LED Support

The Am79C971 controller can support up to four LEDs.

LED outputs LED0, LED1, and LED2 allow for direct

connection of an LED and its supporting pullup device.

In applications that want to use the pin to drive an LED

and also have an EEPROM, it might be necessary to

buffer the LED3 circuit from the EEPROM connection.

When an LED circuit is directly connected to the

EEDO/LED3/SRD pin, then it is not possible for most

EEPROM devices to sink enough IOL to maintain a valid

low level on the EEDO input to the Am79C971 control-

ler.

Each LED can be programmed through a BCR register

to indicate one or more of the following network status

or activities: Collision Status, Full-Duplex Link Status,

Half-Duplex Link Status, Jabber Status, Receive

Match, Receive Polarity, Receive Status, Magic Packet,

Disable Transceiver, MII Enable Status, and Transmit

Status. The LED pins can be configured to operate in

either open-drain mode (active low) or in totem-pole

mode (active high). The output can be stretched to

allow the human eye to recognize even short events

that last only several microseconds. After H_RESET,

the four LED outputs are configured as shown in Table

14:

Table 14.

LED Default Configuration

For each LED register, each of the status signals is

AND’d with its enable signal, and these signals are all

OR’d together to form a combined status signal. Each

LED pin combined status signal can be programmed to

run to a pulse stretcher, which consists of a 3-bit shift

each shift register is normally at logic 0. The OR gate

output for each LED register asynchronously sets all

three bits of its shift register when the output becomes

asserted. The inverted output of each shift register is

used to control an LED pin. Thus, the pulse stretcher

provides 2 to 3 clocks of stretched LED output, or 52

ms to 78 ms. See Figure 54.

Figure 54.

LED Control Logic

Power Savings Modes

SLEEP Mode

The Am79C971 controller supports two hardware

power savings modes. Both are entered by driving the

SLEEP pin LOW and by leaving the MPMODE (CSR 5,

bit 1) bit at its default value of 0.

The power down mode that yields the most power sav-

ings is called, coma mode. In coma mode, the entire

device is shut down. All inputs are ignored except the

SLEEP pin itself. Coma mode is enabled when AWAKE

(BCR2, bit 2) is at its default value of 0 and SLEEP is

asserted.

The second power saving mode is called, snooze

mode. In snooze mode, enabled by setting AWAKE to

1 and driving the SLEEP pin LOW, the T-MAU receive

LED

Output

Indication

Driver Mode

Pulse Stretch

LED0

Link Status

Open Drain -

Active Low

Enabled

LED1

Receive

Status

Open Drain -

Active Low

Enabled

LED2

Receive

Polarity

Open Drain -

Active Low

Enabled

LED3

Transmit

Status

Open Drain -

Active Low

Enabled

COL

COLE

FDLS

FDLSE

JAB

JABE

LNKST

LNKSE

RCV

RCVE

RCVM

RCVME

RXPOL

RXPOLE

XMT

XMTE

PULSE

STRETCHER

ledctrl.eps

MII_SEL

MIISE

MR_SPEED_SEL

100E

MPS

MPSE

LNKST

DXCVRCTL

20550D-57

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