AM79C971VCW datasheet(75/265 Pages) AMD

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Am79C971

General Purpose Serial Interface

The General Purpose Serial Interface (GPSI) provides

a direct interface to the MAC section of the Am79C971

controller. All signals are digital and data is non-en-

coded. The GPSI allows use of an external Manchester

encoder/decoder such as the Am7992B Serial Inter-

face Adapter (SIA). In addition, it allows the Am79C971

controller to be used as a MAC sublayer engine in re-

p eate r de signs based o n t he IM R+ d e vi c e

(Am79C981).

GPSI mode is invoked by selecting the interface

through the PORTSEL bits of the Mode register

(CSR15, bits 8-7).

The GPSI interface uses some of the same pins as the

interface to the MII. Simultaneous use of both functions

is not possible.

After an H_RESET, all MII pins are internally config-

ured to function as the MII interface. When the GPSI in-

terface is selected by setting PORTSEL (CSR15, bits

8-7) to 10b, the Am79C971 controller will terminate all

further accesses to the MII.

GPSI signal functions are described in the pin descrip-

tion section under the GPSI subheading.

Note that the XTAL1 input must always be driven with a

clock source, even if GPSI mode is to be used. It is not

necessary for the XTAL1 clock to meet the normal fre-

quency and stability requirements in this case. Any fre-

quency between 8 MHz and 20 MHz is acceptable.

However, voltage drive requirements do not change.

When GPSI mode is used, XTAL1 must be driven for

several reasons:

The default H_RESET configuration for the Am79C971

controller is AUI port selected. Until GPSI mode is se-

lected, the XTAL1 clock is needed for some internal op-

erations (namely, RESET). The XTAL1 clock drives the

EEPROM read operation, regardless of the network

mode selected.

The XTAL1 clock determines the length of the internal

S_RESET caused by the read of the Reset register, re-

gardless of the network mode.

Note: If a clock slower than 20 MHz is provided at the

XTAL1 input, the time needed for EEPROM read and

the internal S_RESET will increase.

Figure 37.

10BASE-T Interface Connection

Full-Duplex Operation

The Am79C971 controller supports full-duplex opera-

tion on all four network interfaces: AUI, GPSI, 10BASE-

T, and MII. Full-duplex operation allows simultaneous

transmit and receive activity on the TXD

± and RXD±

pairs of the 10BASE-T port, the DO

± and DI± pairs of

the AUI port, TXDAT and RXDAT pins of the GPSI port,

and the TXD[3:0] and RXD[3:0] pins of the MII port.

Full-duplex operation is enabled by the FDEN and

AUIFD bits located in BCR9 for all ports. Full-duplex

operation is enabled through Auto-Negotiation when

DANAS (BCR 32, bit 7) is not enabled on the MII port

or when Auto-Negotiation is running on the internal

PHY.

When operating in full-duplex mode, the following

changes to the device operation are made:

Bus Interface/Buffer Management Unit changes:

s The first 64 bytes of every transmit frame are not

preserved in the Transmit FIFO during transmission

of the first 512 bits as described in the Transmit Ex-

ception Conditions section. Instead, when full-du-

pl ex mo de i s a c t i ve an d a fr am e i s b e in g

XMT

Filter

RCV

Filter

RJ45

Connector

Filter &

Transformer

Module

TXP+

TXD-

TXP-

TXD+

RXD+

RXD-

Am79C971

TD+

TD-

RD+

RD-

61.9

Ω

422

Ω

61.9

Ω

422

Ω

100

Ω

1.21 K

Ω

1:1

20550D-40

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