AM79C971VCW datasheet(52/265 Pages) AMD

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Am79C971

Burst FIFO DMA Transfers

Bursting is only performed by the Am79C971 controller

if the BREADE and/or BWRITE bits of BCR18 are set.

These bits individually enable/disable the ability of the

Am79C971 controller to perform burst accesses during

master read operations and master write operations,

respectively.

A burst transaction will start with an address phase, fol-

lowed by one or more data phases. AD[1:0] will always

be 0 during the address phase indicating a linear burst

order.

During FIFO DMA read operations, all byte lanes will

always be active. The Am79C971 controller will inter-

nally discard unused bytes. During the first and the last

data phases of a FIFO DMA burst write operation, one

or more of the byte enable signals may be inactive. All

other data phases will always write a complete DWord.

Figure 29 shows the beginning of a FIFO DMA write

with the beginning of the buffer not aligned to a DWord

boundary. The Am79C971 controller starts off by writ-

ing only three bytes during the first data phase. This op-

eration aligns the address for all other data transfers to

a 32-bit boundary so that the Am79C971 controller can

continue bursting full DWords.

If a receive buffer does not end on a DWord boundary,

the Am79C971 controller will perform a non-DWord

write on the last transfer to the buffer. Figure 30 shows

the final three FIFO DMA transfers to a receive buffer.

Since there were only nine bytes of space left in the re-

ceive buffer, the Am79C971 controller bursts three data

phases. The first two data phases write a full DWord,

the last one only writes a single byte.

Note that the Am79C971 controller will always perform

a DWord transfer as long as it owns the buffer space,

even when there are less then four bytes to write. For

example, if there is only one byte left for the current re-

ceive frame, the Am79C971 controller will write a full

DWord, containing the last byte of the receive frame in

the least significant byte position (BSWP is cleared to

0, CSR3, bit 2). The content of the other three bytes is

undefined. The message byte count in the receive de-

scriptor always reflects the exact length of the received

frame.

If the end of a receive buffer is not aligned to a DWord

boundary, IWAIT (BCR18, bit 10) must stay at its de-

fault value of 0. This will result in one wait state added

to every data phase in a burst write transaction. When

the software ensures that all receive buffers end on a

DWord boundary, IWAIT can be set to 1. In this mode,

the Am79C971 controller will only insert a wait state in

the first data phase of the burst write transaction.

Figure 29.

FIFO Burst Write At Start Of Unaligned

Buffer

In a PCI bus application, the Am79C971 controller

should be set up to have the length of a bus mastership

period be controlled only by the PCI Latency Timer.

The Timer bit (CSR4, bit 13) should remain at its de-

fault value of 0. In this mode, the Am79C971 controller

will continue transferring FIFO data until the transmit

FIFO is filled to its high threshold (read transfers) or the

receive FIFO is emptied to its low threshold (write

transfers), or the Am79C971 controller is preempted,

and the PCI Latency Timer is expired. The host should

use the values in the PCI MIN_GNT and MAX_LAT reg-

isters to determine the value for the PCI Latency Timer.

In applications that do not use the PCI Latency Timer

or that do not support preemption, the following rules

apply to limit the time the Am79C971 controller takes

on the bus:

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

23456

0000

0111

PAR

DEVSEL is sampled

0001

PAR

DATA

ADD

20550D-32

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