AM79C971VCW datasheet(36/265 Pages) AMD

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Am79C971

Figure 10.

Slave Cycle Data Parity Error Response

Master Bus Interface Unit

The master Bus Interface Unit (BIU) controls the acqui-

sition of the PCI bus and all accesses to the initializa-

tion block, descriptor rings, and the receive and

transmit buffer memory. Table 3 shows the usage of

PCI commands by the Am79C971controller in master

mode.

Bus Acquisition

The Am79C971microcode will determine when a DMA

transfer should be initiated. The first step in any

Am79C971bus master transfer is to acquire ownership

of the bus. This task is handled by synchronous logic

within the BIU. Bus ownership is requested with the

REQ signal and ownership is granted by the arbiter

through the GNT signal.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

ADDR

CMD

PAR

2345678

DATA

PAR

PERR

20550D-13

Table 3.

Master Commands

C[3:0]

Command

Use

0000

Interrupt

Acknowledge

Not used

0001

Special Cycle

Not used

0010

I/O Read

Not used

0011

I/O Write

Not used

0100

Reserved

0101

Reserved

0110

Memory Read

Read of the initialization

block and descriptor

rings

Read of the transmit

buffer in non-burst mode

C[3:0]

Command

Use

0111

Memory Write

Write to the descriptor

rings and to the receive

buffer

1000

Reserved

1001

Reserved

1010

Configuration Read

Not used

1011

Configuration Write

Not used

1100

Memory Read

Multiple

Read of the transmit

buffer in burst mode

1101

Dual Address Cycle Not used

1110

Memory Read Line

Read of the transmit

buffer in burst mode

1111

Memory Write

Invalidate

Not used

Table 3.

Master Commands (Continued)

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