AM79C971VCW datasheet(46/265 Pages) AMD

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Am79C971

Whenever the Am79C971 controller is the current bus

master and a data parity error occurs, SINT (CSR5, bit

11) will be set to 1. When SINT is set, INTA is asserted

if the enable bit SINTE (CSR5, bit 10) is set to 1. This

mechanism can be used to inform the driver of the sys-

tem error. The host can read the PCI Status register to

determine the exact cause of the interrupt. The setting

of SINT due to a data parity error is not dependent on

the setting of PERREN (PCI Command register, bit 6).

By default, a data parity error does not affect the state

of the MAC engine. The Am79C971 controller treats the

data in all bus master transfers that have a parity error

as if nothing has happened. All network activity contin-

ues.

Advanced Parity Error Handling

For all DMA cycles, the Am79C971 controller provides

a second, more advanced level of parity error handling.

This mode is enabled by setting APERREN (BCR20, bit

10) to 1. When APERREN is set to 1, the BPE bits

(RMD1 and TMD1, bit 23) are used to indicate parity

error in data transfers to the receive and transmit buff-

ers. Note that since the advanced parity error handling

uses an additional bit in the descriptor, SWSTYLE

(BCR20, bits 7-0) must be set to 2 or 3 to program the

Am79C971 controller to use 32-bit software structures.

The Am79C971 controller will react in the following way

when a data parity error occurs:

s Initialization block read: STOP (CSR0, bit 2) is set to

1 and causes a STOP_RESET of the device.

s Descriptor ring read: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bit 2) is set to 1 to cause a STOP_RESET

of the device.

s Descriptor ring write: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bit 2) is set to 1 to cause a STOP_RESET

of the device.

s Transmit buffer read: BPE (TMD1, bit 23) is set in

the current transmit descriptor. Any on-going net-

work transmission is terminated in an orderly se-

quence.

s Receive buffer write: BPE (RMD1, bit 23) is set in

the last receive descriptor associated with the frame.

Terminating on-going network transmission in an order-

ly sequence means that if less than 512 bits have been

transmitted onto the network, the transmission will be

terminated immediately, generating a runt packet.

Figure 23.

Initialization Block Read In Non-Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

IADDi

0000

0110

PAR

DATA

IADDi+4

0000

0110

PAR

2345678

20550D-26

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