AM79C971VCW datasheet(23/265 Pages) AMD

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Am79C971

EBDA[15:8]

Expansion Bus Data/Address [15:8]

Input/Output

When ERAMCS is asserted, EBDA[15:8] contain the

data bits [15:8] for SRAM accesses. When EROMCS is

asserted low, EBDA[15:8] contain address bits [15:8]

for boot device accesses.

The EBDA[15:8] signals are driven to a constant level

to conserve power while no access on the Expansion

Bus is being performed.

EBD[7:0]

Expansion Bus Data [7:0]

Input/Output

The EBD[7:0] pins provide data bits [7:0] for RAM/ROM

accesses. The EBD[7:0] signals are internally forced to

a constant level to conserve power while no access on

the Expansion Bus is being performed.

EROMCS

Expansion ROM Chip Select

Output

EROMCS serves as the chip select for the boot device.

It is asserted low during the data phases of boot device

accesses.

ERAMCS

Expansion RAM Chip Select

Output

ERAMCS is asserted during SRAM read and write op-

erations on the expansion bus.

AS_EBOE

Address Strobe/Expansion Bus

Output Enable

Output

AS_EBOE functions as the address strobe for the

upper address bits on the EBUA_EBA[7:0] pins and as

the output enable for the Expansion Bus.

As an address strobe, a rising edge on AS_EBOE is

supplied at the beginning of SRAM and boot device

accesses. This rising edge provides a clock edge for a

‘374 D-type edge-triggered flip-flop which must store

the upper address byte during Expansion Bus ac-

cesses for EPROM/Flash/SRAM.

AS_EBOE is asserted active LOW during boot device

and SRAM read operations on the expansion bus and

is deasserted during boot device and SRAM write

operations.

EBWE

Expansion Bus Write Enable

Output

EBWE provides the write enable for write accesses to

the SRAM devices and/or Flash device.

EBCLK

Expansion Bus Clock

Input

EBCLK may be used as the fundamental clock to drive

the Expansion Bus access cycles. The actual internal

clock used to drive the Expansion Bus cycles depends

on the values of the EBCS and CLK_FAC settings in

BCR27. Refer to the SRAM Interface Bandwidth Re-

quirements section for details on determining the re-

quired EBCLK frequency. If a clock source other than

the EBCLK pin is programmed (BCR27, bits 5:3) to be

used to run the Expansion Bus interface, this input

should be tied to VDD through a 4.7 k

Ω resistor.

EBCLK is not used to drive the bus interface, internal

buffer management unit, or the network functions.

Media Independent Interface

TX_CLK

Transmit Clock

Input

TX_CLK is a continuous clock input that provides the

timing reference for the transfer of the TX_EN,

TXD[3:0], and TX_ER signals out of the Am79C971

device. TX_CLK must provide a nibble rate clock (25%

of the network data rate). Hence, an MII transceiver op-

erating at 10 Mbps must provide a TX_CLK frequency

of 2.5 MHz and an MII transceiver operating at 100

Mbps must provide a TX_CLK frequency of 25 MHz.

Note: The TX_CLK pin is multiplexed with the TXCLK

pin.

When RST is active, TX_CLK is an input for NAND tree

testing.

If the MII port is not selected, the TX_CLK pin can be

left floating.

TXD[3:0]

Transmit Data

Output

TXD[3:0] is the nibble-wide MII transmit data bus. Valid

data is generated on TXD[3:0] on every TX_CLK rising

edge while TX_EN is asserted. While TX_EN is de-

asserted, TXD[3:0] values are driven to a 0. TXD[3:0]

transitions synchronous to TX_CLK rising edges.

Note: The TXD[0] pin is multiplexed with the TXDAT

pin.

When RST is active, TXD[3:0] are inputs for NAND tree

testing.

If the MII port is not selected, the TXD[3:0] pins can be

left floating.

TX_EN

Transmit Enable

Output

TX_EN indicates when the Am79C971 device is pre-

senting valid transmit nibbles on the MII. While TX_EN

is asserted, the Am79C971 device generates TXD[3:0]

and TX_ER on TX_CLK rising edges. TX_EN is as-

serted with the first nibble of preamble and remains as-

serted throughout the duration of a packet until it is

deasserted prior to the first TX_CLK following the final

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